Datasheet LTC3853 (Analog Devices) - 8

LTC3853
PIN FUNCTIONS SENSE1+, SENSE2+, SENSE3+ (Pins 3, 5, 7):
Current Sense
INTVCC (Pin 22):
Internal 5V Regulator Output. The Comparator Inputs. The (+) inputs to the current compara- control circuits are powered from this voltage. Also tors are normally connected to DCR sensing networks or provides channel 3 driver power. Decouple this pin to current sensing resistors. SENSE3+ common modes up PGND with a minimum of 4.7µF low ESR tantalum or to 13.5V, allowing higher VOUT voltages on channel 3. ceramic capacitor.
SENSE1–, SENSE2–, SENSE3– (Pins 4, 6, 8):
Current
EXTVCC (Pin 23):
External Power Input to an Internal Switch Sense Comparator Inputs. The (–) inputs to the current Connected to INTVCC. This switch closes and supplies the comparators are connected to the outputs. SENSE3– com- IC power, bypassing the internal low dropout regulator, mon modes up to 13.5V, allowing higher VOUT voltages whenever EXTVCC is higher than 4.7V. Do not exceed 6V on channel 3. on this pin and ensure VIN > VEXTVCC at all times.
VFB1, VFB2, VFB3 (Pins 9, 12, 14):
Error Amplifier Feedback
VIN (Pin 24):
Main Input Supply. Decouple this pin to Inputs. These pins receive the remotely sensed feedback PGND with a capacitor (0.1µF to 1µF). voltages for each channel from external resistive dividers
DRV
across the outputs. Connecting V
CC12 (Pin 29):
Driver Voltage Input for Channels 1 and FB2 to VIN through a 200k 2. Do not exceed 6V on this pin. This pin must be tied to resistor enables dual output (2 + 1) mode. INTVCC externally.
ITH1, ITH2, ITH3 (Pins 10, 13, 15):
Current Control Thresh-
BG1, BG2, BG3 (Pins 30, 28, 21):
Bottom Gate Driver olds and Error Amplifier Compensation Points. Each as- Outputs. These pins drive the gates of the bottom N- sociated channels’ current comparator tripping threshold channel MOSFETs between PGND and INTV increases with its I CC/DRVCC12. TH control voltage. In dual output (2 + 1) mode, ITH1 and ITH2 need to be shorted externally.
SW1, SW2, SW3 (Pins 31, 27, 20):
Switch Node Con- nections to Inductors. Voltage swing at these pins is
SGND (Pin 11):
Signal Ground. All small-signal compo- from a Schottky diode (external) voltage drop below nents and compensation components should connect to ground to V this ground, which in turn connects to PGND at one point. IN.
TG1, TG2, TG3 (Pins 32, 26, 19):
Top Gate Driver Outputs.
PGOOD3 (Pin 16):
Power Good Indicator Output for Phase These are the outputs of floating drivers with a voltage 3. Open-drain logic out that is pulled to ground when any swing equal to INTV channel output exceeds the ±7.5% regulation window, CC superimposed on the switch nodes voltages. after the internal 17µs power bad mask timer expires.
BOOST1, BOOST2, BOOST3 (Pins 33, 25, 18):
Boosted
PGOOD12 (Pin 17):
Power Good Indicator Output for Floating Driver Supplies. The (+) terminal of the boot- Phases 1 and 2. Open-drain logic out that is pulled to strap capacitors connect to these pins. These pins swing ground when any channel output exceeds the ±7.5% from a diode voltage drop below INTV regulation window, after the internal 17µs power bad CC up to VIN + INTV mask timer expires. CC. 3853fc 8 For more information www.linear.com/LTC3853 Document Outline Features Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts