Datasheet LTC3737 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Dual 2-Phase, No RSENSE DC/DC Controller with Output Tracking |
| Pages / Page | 24 / 6 — PI FU CTIO S (QFN/SSOP). ITH1, ITH2 (Pins 1, 8/Pins 4, 11):. PGND (Pin … |
| File Format / Size | PDF / 282 Kb |
| Document Language | English |
PI FU CTIO S (QFN/SSOP). ITH1, ITH2 (Pins 1, 8/Pins 4, 11):. PGND (Pin 16/Pin 19):. PGATE1, PGATE2 (Pins 17, 15/Pins 20, 18):
Model Line for this Datasheet
Text Version of Document
LTC3737
U U U PI FU CTIO S (QFN/SSOP) ITH1, ITH2 (Pins 1, 8/Pins 4, 11):
Current Threshold and
PGND (Pin 16/Pin 19):
Power Ground. This pin serves as Error Amplifier Compensation Point. Nominal operating the ground connection for the gate drivers. range on these pins is from 0.7V to 2V. The voltage on this
PGATE1, PGATE2 (Pins 17, 15/Pins 20, 18):
Gate Drives pin determines the threshold of the main current for External P-Channel MOSFETs. These pins have an comparator. output swing from PGND to SENSE+.
PLLLPF (Pin 3/Pin 6):
Frequency Set/PLL Lowpass Filter.
SYNC/MODE (Pin 18/Pin 21):
External Clock Synchroni- When synchronizing to an external clock, this pin serves as zation and Burst Mode/Pulse Skipping Select. Applying a the lowpass filter point for the phase-locked loop. Nor- clock with frequency between 250kHz to 850kHz causes mally, a series RC is connected between this pin and the internal oscillator to phase lock to the external clock, ground. and disables Burst Mode operation but allows pulse skip- When not synchronizing to an external clock, this pin serves ping at low load currents. Forcing this pin high enables as the frequency select input. Tying this pin to GND selects Burst Mode operation. Forcing this pin low enables pulse- 300kHz operation; tying this pin to VIN selects 750kHz skipping mode. In these cases, the frequency of the operation. Floating this pin selects 550kHz operation. internal oscillator is set by the voltage on the PLLLPF pin. Do not let this pin float.
SGND (Pin 4/Pin 7):
Signal Ground. This pin serves as the ground connection for most internal circuits.
PVIN1, PVIN2 (Pins 20, 12/Pins 23, 15):
Powers of the Gate Drivers.
VIN (Pin 5/Pin 8):
Chip Signal Power Supply. This pin powers the entire chip except for the gate drivers. Exter-
SENSE1+, SENSE2+ (Pins 21, 11/Pins 24, 14):
Positive nally filtering this pin with a lowpass RC network (e.g., R Inputs to Differential Current Comparators. Normally con- = 10Ω, C = 1µF) is suggested to minimize noise pickup, nected to the sources of the external P-channel MOSFETs. especially in high load current applications.
SW1 (SENSE1–), SW2 (SENSE2–) (Pins 22, 10/Pins 1, TRACK (Pin 6/Pin 9):
Tracking Input for Second Control-
13):
Switch Node Connections to Inductors. Also the ler. This pin allows the start-up of VOUT2 to “track” that of negative inputs to differential peak current comparators. VOUT1 according to a ratio established by a resistor divider Normally connected to the drains of the external P-Chan- on VOUT1 connected to the TRACK pin. For one-to-one nel MOSFETs and the inductor when not using a sense tracking of VOUT1 and VOUT2 during start-up, a resistor resistor. When a sense resistor is used, it will be con- divider with values equal to those connected to VFB2 from nected between SW and SENSE+. VOUT2 should be used to connect to TRACK from VOUT1.
IPRG1, IPRG2 (Pins 23, 2/Pins 2, 5):
Three-State Pins to
PGOOD (Pin 9/Pin 12):
Power Good Output Voltage Moni- Select Maximum Peak Sense Voltage Threshold. These tor Open-Drain Logic Output. This pin is pulled to ground pins select the maximum allowed voltage drop between when the voltage on either feedback pin (VFB1, VFB2) is not the SENSE+ and SW pins (i.e., the maximum allowed drop within ±13.3% of its nominal set point. across the external P-channel MOSFET) for each channel. Tie high, low or float to select 204mV, 85mV or 125mV,
NC (Pins 13, 19/Pins 16, 22):
No Connect. respectively.
RUN/SS (Pin 14/Pin 17):
Run Control Input and Optional
V
External Soft-Start Input. Forcing this pin below 0.65V
FB1, VFB2 (Pins 24, 7/Pins 3, 10):
Each receives the remotely sensed feedback voltage for its controller from shuts down the chip (both channels). Driving this pin to an external resistive divider across the output. VIN or releasing this pin enables the chip to start-up with the internal soft-start. An external soft-start can be pro-
Exposed Pad (Pin 25/NA):
Exposed Pad is PGND and grammed by connecting a capacitor between this pin and must be soldered to PCB. ground. 3737fa 6
U U U PI FU CTIO S (QFN/SSOP) ITH1, ITH2 (Pins 1, 8/Pins 4, 11):
Current Threshold and
PGND (Pin 16/Pin 19):
Power Ground. This pin serves as Error Amplifier Compensation Point. Nominal operating the ground connection for the gate drivers. range on these pins is from 0.7V to 2V. The voltage on this
PGATE1, PGATE2 (Pins 17, 15/Pins 20, 18):
Gate Drives pin determines the threshold of the main current for External P-Channel MOSFETs. These pins have an comparator. output swing from PGND to SENSE+.
PLLLPF (Pin 3/Pin 6):
Frequency Set/PLL Lowpass Filter.
SYNC/MODE (Pin 18/Pin 21):
External Clock Synchroni- When synchronizing to an external clock, this pin serves as zation and Burst Mode/Pulse Skipping Select. Applying a the lowpass filter point for the phase-locked loop. Nor- clock with frequency between 250kHz to 850kHz causes mally, a series RC is connected between this pin and the internal oscillator to phase lock to the external clock, ground. and disables Burst Mode operation but allows pulse skip- When not synchronizing to an external clock, this pin serves ping at low load currents. Forcing this pin high enables as the frequency select input. Tying this pin to GND selects Burst Mode operation. Forcing this pin low enables pulse- 300kHz operation; tying this pin to VIN selects 750kHz skipping mode. In these cases, the frequency of the operation. Floating this pin selects 550kHz operation. internal oscillator is set by the voltage on the PLLLPF pin. Do not let this pin float.
SGND (Pin 4/Pin 7):
Signal Ground. This pin serves as the ground connection for most internal circuits.
PVIN1, PVIN2 (Pins 20, 12/Pins 23, 15):
Powers of the Gate Drivers.
VIN (Pin 5/Pin 8):
Chip Signal Power Supply. This pin powers the entire chip except for the gate drivers. Exter-
SENSE1+, SENSE2+ (Pins 21, 11/Pins 24, 14):
Positive nally filtering this pin with a lowpass RC network (e.g., R Inputs to Differential Current Comparators. Normally con- = 10Ω, C = 1µF) is suggested to minimize noise pickup, nected to the sources of the external P-channel MOSFETs. especially in high load current applications.
SW1 (SENSE1–), SW2 (SENSE2–) (Pins 22, 10/Pins 1, TRACK (Pin 6/Pin 9):
Tracking Input for Second Control-
13):
Switch Node Connections to Inductors. Also the ler. This pin allows the start-up of VOUT2 to “track” that of negative inputs to differential peak current comparators. VOUT1 according to a ratio established by a resistor divider Normally connected to the drains of the external P-Chan- on VOUT1 connected to the TRACK pin. For one-to-one nel MOSFETs and the inductor when not using a sense tracking of VOUT1 and VOUT2 during start-up, a resistor resistor. When a sense resistor is used, it will be con- divider with values equal to those connected to VFB2 from nected between SW and SENSE+. VOUT2 should be used to connect to TRACK from VOUT1.
IPRG1, IPRG2 (Pins 23, 2/Pins 2, 5):
Three-State Pins to
PGOOD (Pin 9/Pin 12):
Power Good Output Voltage Moni- Select Maximum Peak Sense Voltage Threshold. These tor Open-Drain Logic Output. This pin is pulled to ground pins select the maximum allowed voltage drop between when the voltage on either feedback pin (VFB1, VFB2) is not the SENSE+ and SW pins (i.e., the maximum allowed drop within ±13.3% of its nominal set point. across the external P-channel MOSFET) for each channel. Tie high, low or float to select 204mV, 85mV or 125mV,
NC (Pins 13, 19/Pins 16, 22):
No Connect. respectively.
RUN/SS (Pin 14/Pin 17):
Run Control Input and Optional
V
External Soft-Start Input. Forcing this pin below 0.65V
FB1, VFB2 (Pins 24, 7/Pins 3, 10):
Each receives the remotely sensed feedback voltage for its controller from shuts down the chip (both channels). Driving this pin to an external resistive divider across the output. VIN or releasing this pin enables the chip to start-up with the internal soft-start. An external soft-start can be pro-
Exposed Pad (Pin 25/NA):
Exposed Pad is PGND and grammed by connecting a capacitor between this pin and must be soldered to PCB. ground. 3737fa 6
