Datasheet LTC3737 (Analog Devices) - 9

LTC3737
U OPERATIO (Refer to Functional Diagram)
When a controller is in pulse skipping operation, an A phase-locked loop (PLL) is available on the LTC3737 to internal offset at the current comparator input will assure synchronize the internal oscillator to an external clock that the current comparator remains tripped even at zero source that is connected to the SYNC/MODE pin. In this load current and the regulator will start to skip cycles, as case, a series RC should be connected between the it must, in order to maintain regulation. PLLLPF pin and SGND to serve as the PLL’s loop filter. The LTC3737 phase detector adjusts the voltage on the PLLLPF
Short-Circuit Protection
pin to align the turn-on of controller 1’s external P-channel When one of the outputs is shorted to ground (V MOSFET to the rising edge of the synchronizing signal. FB < 0.12V), the switching frequency of that controller is re- Thus, the turn-on of controller 2’s external P-channel duced to 1/3 of the normal operating frequency. The other MOSFET is 180 degrees out of phase to the rising edge of controller is unaffected and maintains normal operation. the external clock source. The short-circuit threshold on V The typical capture range of the LTC3737’s phase-locked FB2 is based on the smaller of 0.12V and a fraction of the voltage on the loop is from approximately 200kHz to 1MHz, with a TRACK pin. This also allows V guarantee over all variations and temperature to be be- OUT2 to start up and track V tween 250kHz and 850kHz. In other words, the LTC3737’s OUT1 more easily. Note that if VOUT1 is truly short circuited (V PLL is guaranteed to lock to an external clock source OUT1 = VFB1 = 0V), then the LTC3737 will try to regulate V whose frequency is between 250kHz and 850kHz. OUT2 to 0V if a resistor divider on VOUT1 is connected to the TRACK pin.
Dropout Operation Output Overvoltage Protection
When the input supply voltage (VIN) decreases towards As a further protection, the overvoltage comparator (OVP) the output voltage, the rate of change of the inductor guards against transient overshoots, as well as other more current while the external P-channel MOSFET is on (ON serious conditions, that may overvoltage the output. When cycle) decreases. This reduction means that the P-channel the feedback voltage on the V MOSFET will remain on for more than one oscillator cycle FB pin has risen 13.33% above the reference voltage of 0.6V, the external P-chan- if the inductor current has not ramped up to the threshold nel MOSFET is turned off until the overvoltage is cleared. set by the EAMP on the ITH pin. Further reduction in the input supply voltage will eventually cause the P-channel
Frequency Selection and Phase-Locked Loop (PLLLPF
MOSFET to be turned on 100%; i.e., DC. The output
and SYNC/MODE Pins)
voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the The selection of switching frequency is a tradeoff between inductor. efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses,
Undervoltage Lockout
but requires larger inductance and/or capacitance to main- tain low output ripple voltage. To prevent operation of the P-channel MOSFET below safe input voltage levels, an undervoltage lockout is incorpo- The switching frequency of the LTC3737’s controllers can rated in the LTC3737. When the input supply voltage (VIN) be selected using the PLLLPF pin. If the SYNC/MODE pin drops below 2.25V, the external P-channel MOSFET and is not being driven by an external clock source, the PLLLPF all internal circuitry are turned off except for the undervolt- pin can be floated, tied to VIN or tied to SGND to select age block, which draws only a few microamperes. 550kHz, 750kHz or 300kHz, respectively. 3737fa 9