Datasheet LTC1702A (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Dual 550kHz Synchronous 2-Phase Switching Regulator Controller |
| Pages / Page | 36 / 6 — PIN FUNCTIONS. FB1 (Pin 12):. VCC (Pin 13):. PGOOD2 (Pin 18):. FB2 (Pin … |
| File Format / Size | PDF / 427 Kb |
| Document Language | English |
PIN FUNCTIONS. FB1 (Pin 12):. VCC (Pin 13):. PGOOD2 (Pin 18):. FB2 (Pin 14):. PGND (Pin 19):. COMP2 (Pin 15):. RUN/SS2 (Pin 16):
Model Line for this Datasheet
Text Version of Document
LTC1702A
U U U PIN FUNCTIONS FB1 (Pin 12):
Controller 1 Feedback Input. FB1 should be turning on the bottom MOSFET switches and pulling down connected through a resistor network to VOUT1 to set the the high output voltage. The LTC1702A will remain latched output voltage. The loop compensation network for con- in this state until the power is cycled. When FAULT mode troller 1 also connects to FB1. is active, the FAULT pin will be pulled up with an internal 10µA current source. Tying FAULT directly to PGND will
VCC (Pin 13):
Power Supply Input. All internal circuits disable latched FAULT mode and will allow the LTC1702A except the output drivers are powered from this pin. VCC to resume normal operation when the overvoltage fault is should be connected to a low noise power supply voltage removed. between 3V and 7V and should be bypassed to SGND with at least a 1µF capacitor in close proximity to the LTC1702A.
PGOOD2 (Pin 18):
Controller 2 Power Good. See PGOOD1.
FB2 (Pin 14):
Controller 2 Feedback Input. See FB1.
PGND (Pin 19):
Power Ground. The BGn drivers return to this pin. Connect PGND to a high current ground node in
COMP2 (Pin 15):
Controller 2 Loop Compensation. See close proximity to the sources of external MOSFETs, QB1 COMP1. and QB2, and the VIN and VOUT bypass capacitors.
RUN/SS2 (Pin 16):
Controller 2 Run/Soft-start. See RUN/
SW2 (Pin 20):
Controller 2 Switching Node. See SW1. SS1.
TG2 (Pin 21):
Controller 2 Top Gate Drive. See TG1.
FAULT (Pin 17):
Output Overvoltage Fault (Latched). The FAULT pin is an open-drain output with an internal 10µA
BG2 (Pin 22):
Controller 2 Bottom Gate Drive. See BG1. pull-up. If either regulated output voltage rises more than
BOOST2 (Pin 23):
Controller 2 Top Gate Driver Supply. 15% above its programmed value for more than 25µs, the See BOOST1. FAULT output will go high and the entire LTC1702A will be disabled. When FAULT is high, both BG pins will go high,
IMAX2 (Pin 24):
Controller 2 Current Limit Set. See IMAX1.
W BLOCK DIAGRAM
FCB PVCC VCC BOOST1,2 BURST TG1,2 LOGIC DRIVE LOGIC SW1,2 BG1,2 90% DUTY CYCLE PGND OSC 1V SGND P-P 550kHz DIS 3.5µA 100µs SOFT PGOOD1,2 RUN/SS1,2 DELAY START COMP1,2 25µs PGOOD DELAY FAULT I 10µA LIM FB + FLT – IMAX1,2 FROM OTHER 800mV 760mV 920mV CONTROLLER FB1,2 SHUTDOWN TO THIS CONTROLLER 1702A BD SHUTDOWN TO 550mV ENTIRE CHIP FROM OTHER CONTROLLER 1702afa 6
U U U PIN FUNCTIONS FB1 (Pin 12):
Controller 1 Feedback Input. FB1 should be turning on the bottom MOSFET switches and pulling down connected through a resistor network to VOUT1 to set the the high output voltage. The LTC1702A will remain latched output voltage. The loop compensation network for con- in this state until the power is cycled. When FAULT mode troller 1 also connects to FB1. is active, the FAULT pin will be pulled up with an internal 10µA current source. Tying FAULT directly to PGND will
VCC (Pin 13):
Power Supply Input. All internal circuits disable latched FAULT mode and will allow the LTC1702A except the output drivers are powered from this pin. VCC to resume normal operation when the overvoltage fault is should be connected to a low noise power supply voltage removed. between 3V and 7V and should be bypassed to SGND with at least a 1µF capacitor in close proximity to the LTC1702A.
PGOOD2 (Pin 18):
Controller 2 Power Good. See PGOOD1.
FB2 (Pin 14):
Controller 2 Feedback Input. See FB1.
PGND (Pin 19):
Power Ground. The BGn drivers return to this pin. Connect PGND to a high current ground node in
COMP2 (Pin 15):
Controller 2 Loop Compensation. See close proximity to the sources of external MOSFETs, QB1 COMP1. and QB2, and the VIN and VOUT bypass capacitors.
RUN/SS2 (Pin 16):
Controller 2 Run/Soft-start. See RUN/
SW2 (Pin 20):
Controller 2 Switching Node. See SW1. SS1.
TG2 (Pin 21):
Controller 2 Top Gate Drive. See TG1.
FAULT (Pin 17):
Output Overvoltage Fault (Latched). The FAULT pin is an open-drain output with an internal 10µA
BG2 (Pin 22):
Controller 2 Bottom Gate Drive. See BG1. pull-up. If either regulated output voltage rises more than
BOOST2 (Pin 23):
Controller 2 Top Gate Driver Supply. 15% above its programmed value for more than 25µs, the See BOOST1. FAULT output will go high and the entire LTC1702A will be disabled. When FAULT is high, both BG pins will go high,
IMAX2 (Pin 24):
Controller 2 Current Limit Set. See IMAX1.
W BLOCK DIAGRAM
FCB PVCC VCC BOOST1,2 BURST TG1,2 LOGIC DRIVE LOGIC SW1,2 BG1,2 90% DUTY CYCLE PGND OSC 1V SGND P-P 550kHz DIS 3.5µA 100µs SOFT PGOOD1,2 RUN/SS1,2 DELAY START COMP1,2 25µs PGOOD DELAY FAULT I 10µA LIM FB + FLT – IMAX1,2 FROM OTHER 800mV 760mV 920mV CONTROLLER FB1,2 SHUTDOWN TO THIS CONTROLLER 1702A BD SHUTDOWN TO 550mV ENTIRE CHIP FROM OTHER CONTROLLER 1702afa 6
