Datasheet ADSP-BF592 (Analog Devices) - 7

ADSP-BF592
initializes the count value of the timer, enables the appropriate
Serial Peripheral Interface (SPI) Ports
interrupt, then enables the timer. Thereafter, the software must The processor has two SPI-compatible ports that enable the reload the counter before it counts to zero from the pro- processor to communicate with multiple SPI-compatible grammed value. This protects the system from remaining in an devices. unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition The SPI interface uses three pins for transferring data: two data or software error. pins (Master Output-Slave Input, MOSI, and Master Input- Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI If configured to generate a hardware reset, the watchdog timer chip select input pin (SPIx_SS) lets other SPI devices select the resets both the core and the processor peripherals. After a reset, processor, and many SPI chip select output pins (SPIx_SEL7–1) software can determine whether the watchdog was the source of let the processor select other SPI devices. The SPI select pins are the hardware reset by interrogating a status bit in the watchdog reconfigured general-purpose I/O pins. Using these pins, the timer control register. SPI port provides a full-duplex, synchronous serial interface, The timer is clocked by the system clock (SCLK) at a maximum which supports both master/slave modes and multimaster frequency of fSCLK. environments.
Timers UART Port
There are four general-purpose programmable timer units in The ADSP-BF592 processor provides a full-duplex universal the processor. Three timers have an external pin that can be asynchronous receiver/transmitter (UART) port, which is fully configured either as a pulse width modulator (PWM) or timer compatible with PC-standard UARTs. The UART port provides output, as an input to clock the timer, or as a mechanism for a simplified UART interface to other peripherals or hosts, measuring pulse widths and periods of external events. These supporting full-duplex, DMA-supported, asynchronous trans- timers can be synchronized to an external clock input to the sev- fers of serial data. The UART port includes support for five to eral other associated PF pins, to an external clock input to the eight data bits, one or two stop bits, and none, even, or odd par- PPI_CLK input pin, or to the internal SCLK. ity. The UART port supports two modes of operation: The timer units can be used in conjunction with the UART to • PIO (programmed I/O) – The processor sends or receives measure the width of the pulses in the data stream to provide a data by writing or reading I/O mapped UART registers. software auto-baud detect function for the respective serial The data is double-buffered on both transmit and receive. channels. • DMA (direct memory access) – The DMA controller trans- The timers can generate interrupts to the processor core provid- fers both transmit and receive data. This reduces the ing periodic events for synchronization, either to the system number and frequency of interrupts required to transfer clock or to a count of external signals. data to and from memory. The UART has two dedicated In addition to the three general-purpose programmable timers, DMA channels, one for transmit and one for receive. These a fourth timer is also provided. This extra timer is clocked by the DMA channels have lower default priority than most DMA internal processor clock and is typically used as a system tick channels because of their relatively low service rates. clock for generation of operating system periodic interrupts.
Parallel Peripheral Interface (PPI) Serial Ports
The processor provides a parallel peripheral interface (PPI) that The ADSP-BF592 processor incorporates two dual-channel can connect directly to parallel analog-to-digital and digital-to- synchronous serial ports (SPORT0 and SPORT1) for serial and analog converters, video encoders and decoders, and other gen- multiprocessor communications. The SPORTs support the fol- eral-purpose peripherals. The PPI consists of a dedicated input lowing features: clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half Serial port data can be automatically transferred to and from the system clock rate, and the synchronization signals can be on-chip memory/external memory via dedicated DMA chan- configured as either inputs or outputs. nels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. In this configura- The PPI supports a variety of general-purpose and ITU-R 656 tion, one SPORT provides two transmit signals while the other modes of operation. In general-purpose mode, the PPI provides SPORT provides the two receive signals. The frame sync and half-duplex, bidirectional data transfer with up to 16 bits of clock are shared. data. Up to three frame synchronization signals are also pro- vided. In ITU-R 656 mode, the PPI provides half-duplex Serial ports operate in five modes: bidirectional transfer of 8- or 10-bit video data. Additionally, • Standard DSP serial mode on-chip decode of embedded start-of-line (SOL) and start-of- • Multichannel (TDM) mode field (SOF) preamble packets is supported. • I2S mode • Packed I2S mode • Left-justified mode Rev. B | Page 7 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide