Datasheet ADSP-BF592 (Analog Devices) - 8

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ADSP-BF592 General-Purpose Mode Descriptions DYNAMIC POWER MANAGEMENT
The general-purpose modes of the PPI are intended to suit a The processor provides five operating modes, each with a differ- wide variety of data capture and transmission applications. ent performance/power profile. In addition, dynamic power Three distinct submodes are supported: management provides the control functions to dynamically alter • Input mode – Frame syncs and data are inputs into the PPI. the processor core supply voltage, further reducing power dissi- Input mode is intended for ADC applications, as well as pation. When configured for a 0 V core supply voltage, the video communication with hardware signaling. processor enters the hibernate state. Control of clocking to each of the processor peripherals also reduces power consumption. • Frame capture mode – Frame syncs are outputs from the See Table 2 for a summary of the power settings for each mode. PPI, but data are inputs. This mode allows the video source(s) to act as a slave (for frame capture for example).
Table 2. Power Settings
• Output mode – Frame syncs and data are outputs from the PPI. Output mode is used for transmitting video or other
Core System
data with up to three output frame syncs.
PLL Clock Clock Core Mode/State PLL Bypassed (CCLK) (SCLK) Power ITU-R 656 Mode Descriptions
Full On Enabled No Enabled Enabled On The ITU-R 656 modes of the PPI are intended to suit a wide Active Enabled/ Yes Enabled Enabled On variety of video capture, processing, and transmission applica- Disabled tions. Three distinct submodes are supported: Sleep Enabled — Disabled Enabled On • Active video only mode – Active video only mode is used Deep Sleep Disabled — Disabled Disabled On when only the active video portion of a field is of interest Hibernate Disabled — Disabled Disabled Off and not any of the blanking intervals. • Vertical blanking only mode – In this mode, the PPI only
Full-On Operating Mode—Maximum Performance
transfers vertical blanking interval (VBI) data. In the full-on mode, the PLL is enabled and is not bypassed, • Entire field mode – In this mode, the entire incoming bit providing capability for maximum operational frequency. This stream is read in through the PPI. is the power-up default execution state in which maximum per-
TWI Controller Interface
formance can be achieved. The processor core and all enabled peripherals run at full speed. The processor includes a 2-wire interface (TWI) module for providing a simple exchange method of control data between
Active Operating Mode—Moderate Dynamic Power
multiple devices. The TWI is functionally compatible with the
Savings
widely used I2C® bus standard. The TWI module offers the In the active mode, the PLL is enabled but bypassed. Because the capabilities of simultaneous master and slave operation and PLL is bypassed, the processor’s core clock (CCLK) and system support for both 7-bit addressing and multimedia data arbitra- clock (SCLK) run at the input clock (CLKIN) frequency. DMA tion. The TWI interface utilizes two pins for transferring clock access is available to appropriately configured L1 memories. (SCL) and data (SDA) and supports the protocol at speeds up to 400K bits/sec. For more information about PLL controls, see the “Dynamic Power Management” chapter in the ADSP-BF59x Blackfin Pro- The TWI module is compatible with serial camera control bus cessor Hardware Reference. (SCCB) functionality for easier control of various CMOS cam- era sensor devices.
Sleep Operating Mode—High Dynamic Power Savings Ports
The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system The processor groups the many peripheral signals to two clock (SCLK), however, continue to operate in this mode. Typi- ports—Port F and Port G. Most of the associated pins are shared cally, an external event wakes up the processor. by multiple signals. The ports function as multiplexer controls. System DMA access to L1 memory is not supported in
General-Purpose I/O (GPIO)
sleep mode. The processor has 32 bidirectional, general-purpose I/O (GPIO)
Deep Sleep Operating Mode—Maximum Dynamic Power
pins allocated across two separate GPIO modules—PORTFIO
Savings
and PORTGIO, associated with Port F and Port G respectively. Each GPIO-capable pin shares functionality with other proces- The deep sleep mode maximizes dynamic power savings by dis- sor peripherals via a multiplexing scheme; however, the GPIO abling the clocks to the processor core (CCLK) and to all functionality is the default state of the device upon power-up. synchronous peripherals (SCLK). Asynchronous peripherals Neither GPIO output nor input drivers are active by default. may still be running but cannot access internal resources or Each general-purpose port pin can be individually controlled by external memory. This powered-down mode can only be exited manipulation of the port control, status, and interrupt registers. by assertion of the reset interrupt (RESET) or by an asynchro- nous interrupt generated by a GPIO pin. Rev. B | Page 8 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide