Datasheet ADSP-BF522C, ADSP-BF523C, ADSP-BF524C, ADSP-BF525C, ADSP-BF526C, ADSP-BF527C (Analog Devices) - 3

ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C GENERAL DESCRIPTION This document describes the differences between the The codec software-programmable stereo output options ADSP-BF52xC and the ADSP-BF52x standard Blackfin® prod- provide the programmer with many application possibilities uct. Please refer to the published ADSP-BF52x data sheet for because the device can be used as a headphone driver or as a general description and specifications. This document only speaker driver. Its volume control functions provide a large describes the differences from that data sheet. range of gain control of the audio signal. The ADSP-BF52xC processors add a low power, high quality
CODEC DESCRIPTION
stereo audio codec for portable digital audio applications with one set of stereo programmable gain amplifier (PGA) line The ADSP-BF52xC codec contains a central clock source, called inputs and one monaural microphone input. It features two 24- the codec master clock (CODEC_MCLK) that produces a refer- bit analog-to-digital converter (ADC) channels and two 24-bit ence clock for all internal audio data processing and synch- digital-to-analog (DAC) converter channels. ronization. When using an external clock source to drive the CODEC_MCLK pin, care should be taken to select a clock The codec can operate as a master or a slave. It supports various source with less than 50 ps of jitter. Without careful generation master clock frequencies, including 12 MHz or 24 MHz for USB of the CODEC_MCLK signal, the digital audio quality devices; standard 256 × fS or 384 × fS based rates, such as will suffer. 12.288 MHz and 24.576 MHz; and many common audio sam- pling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, To enable the codec to generate the central reference clock 24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz. in a system, connect a crystal oscillator between the XTI/ CODEC_MCLK input pin and the XTO output pin. The codec can operate at power supplies as low as 1.8 V for the analog circuitry and as low as 1.8 V for the digital circuitry. The maximum voltage supply is 3.6 V for all supplies.
CSB CSDA CSCL CMODE AVDD CONTROL INTERFACE HPVDD VMID CODEC HPGND AGND MUTE ATTEN/ MUTE MICBIAS VOLUME/ HEADPHONE RHPOUT MUTE DRIVER RLINEIN VOLUME MUTE MUX ADC DAC MUTE
Σ
MUTE ROUT MIC DIGITAL MICIN BOOST FILTERS LOUT MUTE MUX ADC DAC MUTE
Σ
LLINEIN VOLUME MUTE VOLUME/ HEADPHONE LHPOUT MUTE DRIVER ATTEN/ MUTE OSCPD MUTE CLKIN CLKOUT OSC DIGITAL AUDIO INTERFACE DIVIDER DIVIDER XTO T T A OUT DA CLRC A DAC D ADCLRC ADCD CODEC_BCLK CODEC_CLK XTI/CODEC_MCLK
Figure 1. Codec Block Diagram Rev. A | Page 3 of 36 | March 2010 Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide