Datasheet ADSP-BF522C, ADSP-BF523C, ADSP-BF524C, ADSP-BF525C, ADSP-BF526C, ADSP-BF527C (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Blackfin Embedded Processor with Codec |
| Pages / Page | 36 / 6 — DIGITAL AUDIO INTERFACE. 1/fS. LEFT CHANNEL. RIGHT CHANNEL. ADCLRC/. … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
DIGITAL AUDIO INTERFACE. 1/fS. LEFT CHANNEL. RIGHT CHANNEL. ADCLRC/. DACLRC. CODEC_BCLK. ADCDAT/. DACDAT. X = DON’T CARE
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link to page 6 link to page 7 ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C The programmer can simultaneously load the volume control of
DIGITAL AUDIO INTERFACE
both channels by writing to the LRHPBOTH (Register R2, Bit The digital audio input can support the following digital audio D8) and RLHPBOTH (Register R3, Bit D8) bits of the left- or communication protocols: right-justified mode, left-justified right-channel DAC volume registers. mode, I2S mode, and frame sync mode. See Figure 6 on Page 6 The maximum output level of the headphone outputs is through Figure 10 on Page 7. 1.0 V rms when AVDD and HPVDD = 3.3 V. To suppress audi- The mode selection is performed by writing to the FORMAT ble pops and clicks, the headphone and line outputs are held at bits of the digital audio interface register (Register R7, Bit D1 the VMID dc voltage level when the device is set to standby and Bit D0). All modes are MSB first and operate with data of 16 mode or when the headphone outputs are muted. to 32 bits. The stereo line outputs of the codec, the LOUT and ROUT pins, can drive a load impedance of 10 kΩ and 50 pF. The line output signal levels are not adjustable at the output mixer, which has a fixed gain of 0 dB. The maximum output level of the line out- puts is 1.0 V rms when AVDD = 3.3 V.
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ 1 2 3 4 N X X 1 2 3 N X X DACDAT X = DON’T CARE.
Figure 6. Left-Justified Audio Input Mode
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ X X N 4 3 2 1 X X N 4 3 2 1 DACDAT X = DON’T CARE.
Figure 7. Right-Justified Audio Input Mode Rev. A | Page 6 of 36 | March 2010 Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide
DIGITAL AUDIO INTERFACE
both channels by writing to the LRHPBOTH (Register R2, Bit The digital audio input can support the following digital audio D8) and RLHPBOTH (Register R3, Bit D8) bits of the left- or communication protocols: right-justified mode, left-justified right-channel DAC volume registers. mode, I2S mode, and frame sync mode. See Figure 6 on Page 6 The maximum output level of the headphone outputs is through Figure 10 on Page 7. 1.0 V rms when AVDD and HPVDD = 3.3 V. To suppress audi- The mode selection is performed by writing to the FORMAT ble pops and clicks, the headphone and line outputs are held at bits of the digital audio interface register (Register R7, Bit D1 the VMID dc voltage level when the device is set to standby and Bit D0). All modes are MSB first and operate with data of 16 mode or when the headphone outputs are muted. to 32 bits. The stereo line outputs of the codec, the LOUT and ROUT pins, can drive a load impedance of 10 kΩ and 50 pF. The line output signal levels are not adjustable at the output mixer, which has a fixed gain of 0 dB. The maximum output level of the line out- puts is 1.0 V rms when AVDD = 3.3 V.
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ 1 2 3 4 N X X 1 2 3 N X X DACDAT X = DON’T CARE.
Figure 6. Left-Justified Audio Input Mode
1/fS LEFT CHANNEL RIGHT CHANNEL ADCLRC/ DACLRC CODEC_BCLK ADCDAT/ X X N 4 3 2 1 X X N 4 3 2 1 DACDAT X = DON’T CARE.
Figure 7. Right-Justified Audio Input Mode Rev. A | Page 6 of 36 | March 2010 Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide
