Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 4

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ADSP-BF534/ADSP-BF536/ADSP-BF537 BLACKFIN PROCESSOR CORE
instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, As shown in Figure 2, the Blackfin processor core contains two and 8-bit subtract/absolute value/accumulate (SAA) operations. 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, Also provided are the compare/select and vector search four video ALUs, and a 40-bit shifter. The computation units instructions. process 8-, 16-, or 32-bit data from the register file. For certain instructions, two 16-bit ALU operations can be per- The compute register file contains eight 32-bit registers. When formed simultaneously on register pairs (a 16-bit high half and performing compute operations on 16-bit operand data, the 16-bit low half of a compute register). If the second ALU is used, register file operates as 16 independent 16-bit registers. All quad 16-bit operations are possible. operands for compute operations come from the multiported register file and instruction constant fields. The 40-bit shifter can perform shifts and rotates, and is used to support normalization, field extract, and field deposit Each MAC can perform a 16-bit by 16-bit multiply in each instructions. cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation The program sequencer controls the flow of instruction execu- are supported. tion, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and The ALUs perform a traditional set of arithmetic and logical indirect conditional jumps (with static branch prediction), and operations on 16-bit or 32-bit data. In addition, many special subroutine calls. Hardware is provided to support zero-over- instructions are included to accelerate various signal processing head looping. The architecture is fully interlocked, meaning that tasks. These include bit operations such as field extract and pop- the programmer need not manage the pipeline when executing ulation count, modulo 232 multiply, divide primitives, saturation instructions with data dependencies. and rounding, and sign/exponent detection. The set of video
ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 DAG0 P3 P2 DA1 32 P1 DA0 32 P0 Y 32 32 RAB PREG MEMOR TO SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER A0 40 40 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core Rev. J | Page 4 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide