Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 9

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ADSP-BF534/ADSP-BF536/ADSP-BF537
In addition to the dedicated peripheral DMA channels, there are
RTXI RTXO
two memory DMA channels provided for transfers between the various memories of the processor system. This enables trans-
R1
fers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with mini-
X1
mal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or
C1 C2
by a standard register-based autobuffer mechanism. The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors also have an external DMA controller capability via dual external DMA request pins when used in conjunction with the external
SUGGESTED COMPONENTS: X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
bus interface unit (EBIU). This functionality can be used when a
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
high speed interface is required for external FIFOs and high
C1 = 22 pF C2 = 22 pF
bandwidth communications peripherals such as USB 2.0. It
R1 = 10 M
: allows control of the number of data transfers for memDMA.
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
The number of transfers per edge is programmable. This feature
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
can be programmed to allow memDMA to have an increased priority on the external bus relative to the core. Figure 4. External Components for RTC
REAL-TIME CLOCK
general-purpose interrupt, if the timer expires before being reset The real-time clock (RTC) provides a robust set of digital watch by software. The programmer initializes the count value of the features, including current time, stopwatch, and alarm. The timer, enables the appropriate interrupt, then enables the timer. RTC is clocked by a 32.768 kHz crystal external to the Thereafter, the software must reload the counter before it processor. The RTC peripheral has dedicated power supply pins counts to zero from the programmed value. This protects the so that it can remain powered up and clocked even when the system from remaining in an unknown state where software, rest of the processor is in a low power state. The RTC provides which would normally reset the timer, has stopped running due several programmable interrupt options, including interrupt to an external noise condition or software error. per second, minute, hour, or day clock ticks, interrupt on pro- If configured to generate a hardware reset, the watchdog timer grammable stopwatch countdown, or interrupt at a resets both the core and the processor peripherals. After a reset, programmed alarm time. software can determine if the watchdog was the source of the The 32.768 kHz input clock frequency is divided down to a 1 Hz hardware reset by interrogating a status bit in the watchdog signal by a prescaler. The counter function of the timer consists timer control register. of four counters: a 60-second counter, a 60-minute counter, a The timer is clocked by the system clock (SCLK), at a maximum 24-hour counter, and an 32,768-day counter. frequency of fSCLK. When enabled, the alarm function generates an interrupt when
TIMERS
the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is There are nine general-purpose programmable timer units in for a time of day, while the second alarm is for a day and time of the processor. Eight timers have an external pin that can be con- that day. figured either as a pulse-width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for The stopwatch function counts down from a programmed measuring pulse widths and periods of external events. These value, with one-second resolution. When the stopwatch is timers can be synchronized to an external clock input to the sev- enabled and the counter underflows, an interrupt is generated. eral other associated PF pins, to an external clock input to the Like the other peripherals, the RTC can wake up the processor PPI_CLK input pin, or to the internal SCLK. from sleep mode upon generation of any RTC wake-up event. The timer units can be used in conjunction with the two UARTs Additionally, an RTC wake-up event can wake up the processor and the CAN controller to measure the width of the pulses in from deep sleep mode, and wake up the on-chip internal voltage the data stream to provide a software auto-baud detect function regulator from the hibernate operating mode. for the respective serial channels. Connect RTC pins RTXI and RTXO with external components The timers can generate interrupts to the processor core provid- as shown in Figure 4. ing periodic events for synchronization, either to the system
WATCHDOG TIMER
clock or to a count of external signals. The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors In addition to the eight general-purpose programmable timers, include a 32-bit timer that can be used to implement a software a ninth timer is also provided. This extra timer is clocked by the watchdog function. A software watchdog can improve system internal processor clock and is typically used as a system tick availability by forcing the processor to a known state through clock for generating periodic interrupts in an operating system. generation of a system reset, nonmaskable interrupt (NMI), or Rev. J | Page 9 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide