Datasheet ADSP-BF561 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Blackfin Embedded Symmetric Multiprocessor |
| Pages / Page | 64 / 1 — FEATURES. 2 internal memory-to-memory DMAs and 1 internal memory. DMA … |
| Revision | E |
| File Format / Size | PDF / 3.3 Mb |
| Document Language | English |
FEATURES. 2 internal memory-to-memory DMAs and 1 internal memory. DMA controller
Model Line for this Datasheet
Text Version of Document
link to page 4 link to page 20 link to page 20 Blackfin Embedded Symmetric Multiprocessor ADSP-BF561
FEATURES 2 internal memory-to-memory DMAs and 1 internal memory DMA controller Dual symmetric 600 MHz high performance Blackfin cores 12 general-purpose 32-bit timers/counters with PWM 328K bytes of on-chip memory capability (see Memory Architecture on Page 4 ) SPI-compatible port Each Blackfin core includes UART with support for IrDA Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter Dual watchdog timers RISC-like register and instruction model for ease of pro Dual 32-bit core timers gramming and compiler-friendly support 48 programmable flags (GPIO) Advanced debug, trace, and performance monitoring On-chip phase-locked loop capable of 0.5
×
to 64
×
frequency Wide range of operating voltages, (see Operating Conditions multiplication on Page 20) 2 parallel input/output peripheral interface units supporting 256-ball CSP_BGA (2 sizes) and 297-ball PBGA ITU-R 656 video and glueless interface to analog front end package options ADCs 2 dual channel, full duplex synchronous serial ports support PERIPHERALS ing eight stereo I2S channels Dual 12-channel DMA controllers (supporting 24 peripheral DMAs) 2 memory-to-memory DMAs JTAG TEST VOLTA IRQ CONTROL/ REGULA EMULATION WATCHDOG TIMER
B B
UART IrDA SPI L1 L1 L1 L1 INSTRUCTION L2 SRAM DATA INSTRUCTION DATA MEMORY 128K BYTES MEMORY MEMORY MEMORY SPORT0 IMDMA SPORT1 CORE SYSTEM/BUS INTERFACE CONTROLLER GPIO EAB DMA CONTROLLER1 32 TIMERS DMA DEB CONTROLLER2 DAB 16 BOOT ROM 32 PAB 16 DAB EXTERNAL PORT PPI0 PPI1 FLASH/SDRAM CONTROL
Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
FEATURES 2 internal memory-to-memory DMAs and 1 internal memory DMA controller Dual symmetric 600 MHz high performance Blackfin cores 12 general-purpose 32-bit timers/counters with PWM 328K bytes of on-chip memory capability (see Memory Architecture on Page 4 ) SPI-compatible port Each Blackfin core includes UART with support for IrDA Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter Dual watchdog timers RISC-like register and instruction model for ease of pro Dual 32-bit core timers gramming and compiler-friendly support 48 programmable flags (GPIO) Advanced debug, trace, and performance monitoring On-chip phase-locked loop capable of 0.5
×
to 64
×
frequency Wide range of operating voltages, (see Operating Conditions multiplication on Page 20) 2 parallel input/output peripheral interface units supporting 256-ball CSP_BGA (2 sizes) and 297-ball PBGA ITU-R 656 video and glueless interface to analog front end package options ADCs 2 dual channel, full duplex synchronous serial ports support PERIPHERALS ing eight stereo I2S channels Dual 12-channel DMA controllers (supporting 24 peripheral DMAs) 2 memory-to-memory DMAs JTAG TEST VOLTA IRQ CONTROL/ REGULA EMULATION WATCHDOG TIMER
B B
UART IrDA SPI L1 L1 L1 L1 INSTRUCTION L2 SRAM DATA INSTRUCTION DATA MEMORY 128K BYTES MEMORY MEMORY MEMORY SPORT0 IMDMA SPORT1 CORE SYSTEM/BUS INTERFACE CONTROLLER GPIO EAB DMA CONTROLLER1 32 TIMERS DMA DEB CONTROLLER2 DAB 16 BOOT ROM 32 PAB 16 DAB EXTERNAL PORT PPI0 PPI1 FLASH/SDRAM CONTROL
Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
