Datasheet ADSP-BF561 (Analog Devices) - 8

link to page 7 ADSP-BF561 even though the event may be latched in the ILAT register. peripherals. Additionally, DMA transfers can be accomplished This register may be read from or written to while in between any of the DMA-capable peripherals and external supervisor mode. devices connected to the external memory interfaces, including Note that general-purpose interrupts can be globally the SDRAM controller and the asynchronous memory enabled and disabled with the STI and CLI instructions, controller. DMA-capable peripherals include the SPORTs, SPI respectively. port, UART, and PPIs. Each individual DMA-capable periph­ eral has at least one dedicated DMA channel. • CEC Interrupt Pending Register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the The ADSP-BF561 DMA controllers support both 1-dimen­ IPEND register indicates the event is currently active or sional (1-D) and 2-dimensional (2-D) DMA transfers. DMA nested at some level. This register is updated automatically transfer initialization can be implemented from registers or by the controller but may be read while in supervisor mode. from sets of parameters called descriptor blocks. The SIC allows further control of event processing by providing The 2-D DMA capability supports arbitrary row and column six 32-bit interrupt control and status registers. Each register sizes up to 64K elements by 64K elements, and arbitrary row contains a bit corresponding to each of the peripheral interrupt and column step sizes up to ± 32K elements. Furthermore, the events shown in Table 2. column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is • SIC Interrupt Mask Registers (SIC_IMASKx) – These reg­ especially useful in video applications where data can be de- isters control the masking and unmasking of each interleaved on the fly. peripheral interrupt event. When a bit is set in these regis­ ters, that peripheral event is unmasked and will be Examples of DMA types supported by the ADSP-BF561 DMA processed by the system when asserted. A cleared bit in controllers include: these registers masks the peripheral event, thereby prevent­ • A single linear buffer that stops upon completion. ing the processor from servicing the event. • A circular autorefreshing buffer that interrupts on each full • SIC Interrupt Status Registers (SIC_ISRx) – As multiple or fractionally full buffer. peripherals can be mapped to a single event, these registers • 1-D or 2-D DMA using a linked list of descriptors. allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the • 2-D DMA using an array of descriptors, specifying only the peripheral is asserting the interrupt; a cleared bit indicates base DMA address within a common page. the peripheral is not asserting the event. In addition to the dedicated peripheral DMA channels, each • SIC Interrupt Wakeup Enable Registers (SIC_IWRx) – By DMA Controller has four memory DMA channels provided for enabling the corresponding bit in these registers, each transfers between the various memories of the ADSP-BF561 peripheral can be configured to wake up the processor, system. These enable transfers of blocks of data between any of should the processor be in a powered-down mode when the memories—including external SDRAM, ROM, SRAM, and the event is generated. flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor- Because multiple interrupt sources can map to a single general- based methodology or by a standard register-based autobuffer purpose interrupt, multiple pulse assertions can occur simulta­ mechanism. neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND reg­ Further, the ADSP-BF561 has a four channel Internal Memory ister contents are monitored by the SIC as the interrupt DMA (IMDMA) Controller. The IMDMA Controller allows acknowledgement. data transfers between any of the internal L1 and L2 memories. The appropriate ILAT register bit is set when an interrupt rising
WATCHDOG TIMER
edge is detected (detection requires two core clock cycles). The Each ADSP-BF561 core includes a 32-bit timer, which can be bit is cleared when the respective IPEND register bit is set. The used to implement a software watchdog function. A software IPEND bit indicates that the event has entered into the proces­ watchdog can improve system availability by forcing the proces­ sor pipeline. At this point the CEC will recognize and queue the sor to a known state, via generation of a hardware reset, next rising edge event on the corresponding event input. The nonmaskable interrupt (NMI), or general-purpose interrupt, if minimum latency from the rising edge transition of the general- the timer expires before being reset by software. The program­ purpose interrupt to the IPEND output asserted is three core mer initializes the count value of the timer, enables the clock cycles; however, the latency can be much higher, depend­ appropriate interrupt, then enables the timer. Thereafter, the ing on the activity within and the mode of the processor. software must reload the counter before it counts to zero from
DMA CONTROLLERS
the programmed value. This protects the system from remain­ ing in an unknown state where software, which would normally The ADSP-BF561 has two independent DMA controllers that reset the timer, has stopped running due to an external noise support automated data transfers with minimal overhead for condition or software error. the DSP cores. DMA transfers can occur between the ADSP-BF561 internal memories and any of its DMA-capable Rev. E | Page 8 of 64 | September 2009 Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide