Datasheet ADSP-BF561 (Analog Devices) - 9

ADSP-BF561 After a reset, software can determine if the watchdog was the • DMA operations with single-cycle overhead – Each SPORT source of the hardware reset by interrogating a status bit in the can automatically receive and transmit multiple buffers of timer control register, which is set only upon a watchdog gener­ memory data. The DSP can link or chain sequences of ated reset. DMA transfers between a SPORT and memory. The timer is clocked by the system clock (SCLK) at a maximum • Interrupts – Each transmit and receive port generates an frequency of f . interrupt upon completing the transfer of a data word or SCLK after transferring an entire data buffer or buffers through
TIMERS
DMA. There are 14 programmable timer units in the ADSP-BF561. • Multichannel capability – Each SPORT supports 128 chan­ Each of the 12 general-purpose timer units can be indepen­ nels out of a 1,024-channel window and is compatible with dently programmed as a Pulse Width Modulator (PWM), the H.100, H.110, MVIP-90, and HMVIP standards. internally or externally clocked timer, or pulse width counter. An additional 250 mV of SPORT input hysteresis can be The general-purpose timer units can be used in conjunction enabled by setting Bit 15 of the PLL_CTL register. When this bit with the UART to measure the width of the pulses in the data is set, all SPORT input pins have the increased hysteresis. stream to provide an autobaud detect function for a serial chan­ nel. The general-purpose timers can generate interrupts to the
SERIAL PERIPHERAL INTERFACE (SPI) PORT
processor core providing periodic events for synchronization, The ADSP-BF561 processor has an SPI-compatible port that either to the processor clock or to a count of external signals. enables the processor to communicate with multiple SPI-com­ In addition to the 12 general-purpose programmable timers, patible devices. another timer is also provided for each core. These extra timers The SPI interface uses three pins for transferring data: two data are clocked by the internal processor clock (CCLK) and are typ­ pins (master output-slave input, MOSI, and master input-slave ically used as a system tick clock for generation of operating output, MISO) and a clock pin (serial clock, SCK). An SPI chip system periodic interrupts. select input pin (SPISS) lets other SPI devices select the proces­
SERIAL PORTS (SPORTs)
sor, and seven SPI chip select output pins (SPISEL7–1) let the processor select other SPI devices. The SPI select pins are recon­ The ADSP-BF561 incorporates two dual-channel synchronous figured programmable flag pins. Using these pins, the SPI port serial ports (SPORT0 and SPORT1) for serial and multiproces­ provides a full-duplex, synchronous serial interface which sup­ sor communications. The SPORTs support the following ports both master/slave modes and multimaster environments. features: The baud rate and clock phase/polarities for the SPI port are • I2S capable operation. programmable, and it has an integrated DMA controller, con­ • Bidirectional operation – Each SPORT has two sets of inde­ figurable to support transmit or receive data streams. The SPI pendent transmit and receive pins, enabling eight channels DMA controller can only service unidirectional accesses at any of I2S stereo audio. given time. • Buffered (8-deep) transmit and receive ports – Each port The SPI port clock rate is calculated as: has a data register for transferring data words to and from f other DSP components and shift registers for shifting data SCLK SPI Clock Rate = ------------------ in and out of the data registers. 2 × SPI_BAUD Where the 16-bit SPI_BAUD register contains a value of 2 to • Clocking – Each transmit and receive port can either use an 65,535. external serial clock or generate its own, in frequencies During transfers, the SPI port simultaneously transmits and ranging from (f /131,070) Hz to (f /2) Hz. SCLK SCLK receives by serially shifting data in and out on its two serial data • Word length – Each SPORT supports serial data words lines. The serial clock line synchronizes the shifting and sam­ from 3 bits to 32 bits in length, transferred most significant pling of data on the two serial data lines. bit first or least significant bit first.
UART PORT
• Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync The ADSP-BF561 processor provides a full-duplex universal signals can be generated internally or externally, active high asynchronous receiver/transmitter (UART) port, which is fully or low, and with either of two pulse widths and early or late compatible with PC-standard UARTs. The UART port provides frame sync. a simplified UART interface to other peripherals or hosts, sup­ • Companding in hardware – Each SPORT can perform porting full-duplex, DMA-supported, asynchronous transfers of A-law or μ-law companding according to ITU recommen­ serial data. The UART port includes support for 5 data bits to dation G.711. Companding can be selected on the transmit 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd par­ and/or receive channel of the SPORT without additional ity. The UART port supports two modes of operation: latencies. Rev. E | Page 9 of 64 | September 2009 Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide