Datasheet ADAU1401A (Analog Devices) - 7

link to page 7
ADAU1401A DIGITAL TIMING SPECIFICATIONS Table 8. Limit Parameter
1
tMIN tMAX Unit Description
MASTER CLOCK tMP 36 244 ns MCLKI period, 512 × fS mode. tMP 48 366 ns MCLKI period, 384 × fS mode. tMP 73 488 ns MCLKI period, 256 × fS mode. tMP 291 1953 ns MCLKI period, 64 × fS mode. SERIAL PORT tBIL 40 ns INPUT_BCLK low pulse width. tBIH 40 ns INPUT_BCLK high pulse width. tLIS 10 ns INPUT_LRCLK setup; time to INPUT_BCLK rising. tLIH 10 ns INPUT_LRCLK hold; time from INPUT_BCLK rising. tSIS 10 ns SDATA_INx setup; time to INPUT_BCLK rising. tSIH 10 ns SDATA_INx hold; time from INPUT_BCLK rising. tLOS 10 ns OUTPUT_LRCLK setup in slave mode. tLOH 10 ns OUTPUT_LRCLK hold in slave mode. tTS 5 ns OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew. tSODS 40 ns SDATA_OUTx delay in slave mode; time from OUTPUT_BCLK falling. tSODM 40 ns SDATA_OUTx delay in master mode; time from OUTPUT_BCLK falling. SPI PORT fCCLK 6.25 MHz CCLK frequency. tCCPL 80 ns CCLK pulse width low. tCCPH 80 ns CCLK pulse width high. tCLS 0 ns CLATCH setup; time to CCLK rising. tCLH 100 ns CLATCH hold; time from CCLK rising. tCLPH 80 ns CLATCH pulse width high. tCDS 0 ns CDATA setup; time to CCLK rising. tCDH 80 ns CDATA hold; time from CCLK rising. tCOD 101 ns COUT delay; time from CCLK falling. I2C PORT fSCL 400 kHz SCL frequency. tSCLH 0.6 μs SCL high. tSCLL 1.3 μs SCL low. tSCS 0.6 μs SCL setup time, relevant for repeated start condition. tSCH 0.6 μs SCL hold time. After this period, the first clock is generated. tDS 100 ns Data setup time. tSCR 300 ns SCL rise time. tSCF 300 ns SCL fall time. tSDR 300 ns SDA rise time. tSDF 300 ns SDA fall time. tBFT 0.6 Bus-free time; time between stop and start. MULTIPURPOSE PINS AND RESET tGRT 50 ns GPIO rise time. tGFT 50 ns GPIO fall time. tGIL 1.5 × 1/fS μs GPIO input latency; time until high/low value is read by core. tRLPW 20 ns RESET low pulse width. 1 All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 66). Rev. A | Page 7 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address, R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 AND ADDRESS 2075 (0x081A AND 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 AND ADDRESS 2081 (0x0820 AND 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP REGISTER MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS