Datasheet LT8711 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Micropower Synchronous Multitopology Controller with 42V Input Capability |
| Pages / Page | 38 / 8 — PIN FUNCTIONS (TSSOP/QFN) EN/FBIN (Pin 1/Pin 19):. TG (Pin 10/Pin 8):. BG … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
PIN FUNCTIONS (TSSOP/QFN) EN/FBIN (Pin 1/Pin 19):. TG (Pin 10/Pin 8):. BG (Pin 11/Pin 10):. NC (Pin 12/Pin 9):. INTV
Model Line for this Datasheet
Text Version of Document
link to page 9 link to page 1 link to page 1 link to page 14 LT8711
PIN FUNCTIONS (TSSOP/QFN) EN/FBIN (Pin 1/Pin 19):
Enable and Input Voltage Regu-
TG (Pin 10/Pin 8):
PFET Gate Drive Pin. Low and high lation Pin. In conjunction with the UVLO (undervoltage levels are INTVEE and BIAS respectively with a 2A drive lockout) circuit, this pin is used to enable/disable the chip capability. and restart the soft-start sequence. The EN/FBIN pin is
BG (Pin 11/Pin 10):
NFET Gate Drive Pin. Low and high also used to limit the switching regulator current to avoid levels are GND and INTV collapsing the input supply. Drive below 0.2V to disable the CC respectively with a 2A drive capability. chip with very low quiescent current. Drive above 1.03V (typical) to activate the chip. The commanded input cur-
NC (Pin 12/Pin 9):
No Connection. Do not connect. Must rent will adjust when the EN/FBIN pin voltage is between be floated. 1.12V and 1.27V. Drive above 1.35V (typical) to activate
INTV
switching with no reduction in input current and restart the
CC (Pin 13/Pin 12):
5V Dual Input LDO Regulator Pin. Must be locally bypassed with a minimum capacitance of soft-start sequence. See the Block Diagram and Applica- 2.2µF to GND. Logic will choose to run INTV tions section for more information. Do not float this pin. CC from the VIN or EXTVCC pins. A maximum 10mA external load can
FB (Pin 2/Pin 20):
Feedback Input Pin. The LT8711 regu- connect to the INTVCC pin. The undervoltage lockout on lates the FB pin to 0.8V. Connect the feedback resistor INTVCC is 3.6V (typical). The BG gate driver can begin divider tap to this pin. switching when INTVCC exceeds 4.1V (typical).
VC (Pin 3/Pin 1):
Error Amplifier Output Pin. Tie external
VIN (Pin 14/Pin 13):
Input Supply Pin. Must be locally compensation network to this pin. bypassed. Can run down to 0V as long as EXTVCC > 4.5V.
SS (Pin 4/Pin 2):
Soft Start Pin. Place a soft-start capaci-
EXTVCC (Pin 15/Pin 14):
Alternate Input Supply Pin. tor here. Upon start-up, the SS pin will be charged by a Must be locally bypassed. Can run down to 0V as long 410k resistor to about 4.3V. During an overtemperature as VIN > 4.5V. or UVLO condition, the SS pin will be quickly discharged
CSN & CSP (Pins 16 & 17/ Pins 15 & 16):
Current Sense to reset the part. Once those conditions are clear, the part Negative and Positive Input Pins Respectively. Kelvin will attempt to restart. connect CSN and CSP pins to a sense resistor to limit
OPMODE (Pin 5/Pin 3):
Topology Selection Pin. Tie this the input current. The maximum sense voltage at low pin to ground to select buck/ZETA mode. Tie to INTVCC duty cycle is 50mV. to select SEPIC/boost mode. Tie to a 100pF capacitor to
NC (Pin 18/Pin 11):
No Connection. Do not connect. Must GND to select nonsynchronous buck-boost mode. be floated.
ISP & ISN (Pins 6 & 7/ Pins 4 & 5):
Current Sense Posi-
SYNC (Pin 19/Pin 17):
To synchronize the switching tive and Negative Input Pins respectively. Kelvin connect frequency to an outside clock, simply drive this pin with ISP and ISN pins to a sense resistor. a clock. The high voltage level of the clock must exceed
INTVEE (Pin 8/Pin 6):
5V Below BIAS LDO Regulator Pin. 1.3V, and the low level must be less than 0.4V. Drive this Must be locally bypassed with a minimum capacitance pin to less than 0.4V to revert to the internal free running of 2.2µF to BIAS. This pin sets the bottom rail for the TG clock. See the Applications Information section for more gate driver. The TG gate driver can begin switching when information. BIAS – INTVEE exceeds 3.6V (typical).
RT (Pin 20/Pin 18):
Timing Resistor Pin. Adjusts the
BIAS (Pin 9/Pin 7):
Power Supply for the TG PFET Driver. LT8711’s switching frequency. Place a resistor from this Must be locally bypassed with a minimum capacitance of pin to ground to set the frequency to a fixed free running 2.2µF to INTVEE. The BIAS pin sets the top rail for the TG level. Do not float this pin. gate driver.
GND (Pin 21/Pin 21):
Ground. Must be soldered directly to the local ground plane. Rev A 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Start-Up and Fault Sequence Operation Applications Information Appendix Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS (TSSOP/QFN) EN/FBIN (Pin 1/Pin 19):
Enable and Input Voltage Regu-
TG (Pin 10/Pin 8):
PFET Gate Drive Pin. Low and high lation Pin. In conjunction with the UVLO (undervoltage levels are INTVEE and BIAS respectively with a 2A drive lockout) circuit, this pin is used to enable/disable the chip capability. and restart the soft-start sequence. The EN/FBIN pin is
BG (Pin 11/Pin 10):
NFET Gate Drive Pin. Low and high also used to limit the switching regulator current to avoid levels are GND and INTV collapsing the input supply. Drive below 0.2V to disable the CC respectively with a 2A drive capability. chip with very low quiescent current. Drive above 1.03V (typical) to activate the chip. The commanded input cur-
NC (Pin 12/Pin 9):
No Connection. Do not connect. Must rent will adjust when the EN/FBIN pin voltage is between be floated. 1.12V and 1.27V. Drive above 1.35V (typical) to activate
INTV
switching with no reduction in input current and restart the
CC (Pin 13/Pin 12):
5V Dual Input LDO Regulator Pin. Must be locally bypassed with a minimum capacitance of soft-start sequence. See the Block Diagram and Applica- 2.2µF to GND. Logic will choose to run INTV tions section for more information. Do not float this pin. CC from the VIN or EXTVCC pins. A maximum 10mA external load can
FB (Pin 2/Pin 20):
Feedback Input Pin. The LT8711 regu- connect to the INTVCC pin. The undervoltage lockout on lates the FB pin to 0.8V. Connect the feedback resistor INTVCC is 3.6V (typical). The BG gate driver can begin divider tap to this pin. switching when INTVCC exceeds 4.1V (typical).
VC (Pin 3/Pin 1):
Error Amplifier Output Pin. Tie external
VIN (Pin 14/Pin 13):
Input Supply Pin. Must be locally compensation network to this pin. bypassed. Can run down to 0V as long as EXTVCC > 4.5V.
SS (Pin 4/Pin 2):
Soft Start Pin. Place a soft-start capaci-
EXTVCC (Pin 15/Pin 14):
Alternate Input Supply Pin. tor here. Upon start-up, the SS pin will be charged by a Must be locally bypassed. Can run down to 0V as long 410k resistor to about 4.3V. During an overtemperature as VIN > 4.5V. or UVLO condition, the SS pin will be quickly discharged
CSN & CSP (Pins 16 & 17/ Pins 15 & 16):
Current Sense to reset the part. Once those conditions are clear, the part Negative and Positive Input Pins Respectively. Kelvin will attempt to restart. connect CSN and CSP pins to a sense resistor to limit
OPMODE (Pin 5/Pin 3):
Topology Selection Pin. Tie this the input current. The maximum sense voltage at low pin to ground to select buck/ZETA mode. Tie to INTVCC duty cycle is 50mV. to select SEPIC/boost mode. Tie to a 100pF capacitor to
NC (Pin 18/Pin 11):
No Connection. Do not connect. Must GND to select nonsynchronous buck-boost mode. be floated.
ISP & ISN (Pins 6 & 7/ Pins 4 & 5):
Current Sense Posi-
SYNC (Pin 19/Pin 17):
To synchronize the switching tive and Negative Input Pins respectively. Kelvin connect frequency to an outside clock, simply drive this pin with ISP and ISN pins to a sense resistor. a clock. The high voltage level of the clock must exceed
INTVEE (Pin 8/Pin 6):
5V Below BIAS LDO Regulator Pin. 1.3V, and the low level must be less than 0.4V. Drive this Must be locally bypassed with a minimum capacitance pin to less than 0.4V to revert to the internal free running of 2.2µF to BIAS. This pin sets the bottom rail for the TG clock. See the Applications Information section for more gate driver. The TG gate driver can begin switching when information. BIAS – INTVEE exceeds 3.6V (typical).
RT (Pin 20/Pin 18):
Timing Resistor Pin. Adjusts the
BIAS (Pin 9/Pin 7):
Power Supply for the TG PFET Driver. LT8711’s switching frequency. Place a resistor from this Must be locally bypassed with a minimum capacitance of pin to ground to set the frequency to a fixed free running 2.2µF to INTVEE. The BIAS pin sets the top rail for the TG level. Do not float this pin. gate driver.
GND (Pin 21/Pin 21):
Ground. Must be soldered directly to the local ground plane. Rev A 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Start-Up and Fault Sequence Operation Applications Information Appendix Typical Applications Package Description Typical Application Related Parts
