Datasheet CMX655A, CMX655D (CML Microcircuits) - 4
| Manufacturer | CML Microcircuits |
| Description | Ultra Low Power Voice Codec |
| Pages / Page | 79 / 4 — Application Notes ... 57. Performance Specification .. 59 |
| Revision | 3 |
| File Format / Size | PDF / 2.6 Mb |
| Document Language | English |
Application Notes ... 57. Performance Specification .. 59
Model Line for this Datasheet
Text Version of Document
link to page 51 link to page 53 link to page 53 link to page 54 link to page 54 link to page 55 link to page 57 link to page 57 link to page 57 link to page 57 link to page 58 link to page 58 link to page 58 link to page 59 link to page 59 link to page 59 link to page 59 link to page 60 link to page 68 link to page 68 link to page 71 link to page 73 link to page 74 link to page 76 link to page 78 link to page 78 link to page 8 link to page 9 link to page 11 link to page 12 link to page 14 link to page 15 link to page 16 link to page 17 link to page 18 link to page 19 link to page 20 link to page 22 link to page 22 link to page 28 link to page 45 link to page 55 link to page 64 link to page 65 link to page 66 link to page 66 link to page 67 link to page 67 link to page 1 link to page 1 link to page 7 link to page 7 link to page 10 link to page 13 link to page 14 link to page 15 Ultra-Low Power Voice Codec CMX655D/CMX655A 5.8.5 Serial Audio Interface Registers .. 51 5.9 Interrupt Status and IRQN Pin ... 53 5.9.1 Interrupt Registers .. 53 5.10 System Control .. 54 5.10.1 System Control Registers ... 54 5.11 Register Address Map ... 55
6 Application Notes ... 57
6.1 Programming Examples ... 57 6.1.1 Start-up ... 57 6.1.2 DC-offset Calibration ... 57 6.1.3 Configuration ... 58 6.1.4 Enable Audio Channels .. 58 6.1.5 Shutdown .. 58
7 Performance Specification .. 59
7.1 Electrical Performance .. 59 7.1.1 Absolute Maximum Ratings .. 59 7.1.2 Operating Limits .. 59 7.1.3 Operating Characteristics .. 60 7.2 Typical Performance Characteristics ... 68 7.2.1 THD+N vs. Level performance ... 68 7.2.2 THD+N vs. Frequency performance ... 71 7.2.3 Class D Amplifier Efficiency ... 73 7.2.4 Filter Performance Speaker Channel ... 74 7.2.5 Filter Performance Microphone Channel .. 76 7.3 Packaging... 78 7.3.1 CMX655D/CMX655A ... 78 Table Page Table 1 CMX655A Pin List by Number ... 8 Table 2 CMX655A Pin List by Group .. 9 Table 3 CMX655D Pin List by Number ... 11 Table 4 CMX655D Pin List by Group .. 12 Table 5 CMX655A Component Values ... 14 Table 6 CMX655A SPI Component Values ... 15 Table 7 CMX655A TWI Component Values .. 16 Table 8 CMX655A AC Coupling Component Values ... 17 Table 9 CMX655D Component Values ... 18 Table 10 CMX655D SPI Component Value ... 19 Table 11 CMX655D TWI Component Values .. 20 Table 12 External Supply Voltages ... 22 Table 13 Supply and POR Threshold Voltages ... 22 Table 14 Bypass Mode Component Values.. 28 Table 15 CMX655D/CMX655A Slave Addresses .. 45 Table 16 Register Address Map ... 55 Table 17 SPI Timing Parameter Values .. 64 Table 18 TWI Standard Mode Timing Parameters ... 65 Table 19 TWI Fast Mode Timing Parameters ... 66 Table 20 TWI Pull-up Resistors and Bus Capacitance .. 66 Table 21 SAI Timing Parameters .. 67 Table 22 Digital Microphone Timing Parameters .. 67 Figure Page Figure 1 CMX655A Simplified Block Diagram... 1 Figure 2 CMX655D Simplified Block Diagram .. 1 Figure 3 CMX655A Block Diagram ... 7 Figure 4 CMX655D Block Diagram ... 7 Figure 5 CMX655A Pin Arrangement ... 10 Figure 6 CMX655D Pin Arrangement ... 13 Figure 7 CMX655A Power Supply and Pin Decoupling ... 14 Figure 8 CMX655A SPI Connections ... 15 2018 CML Microsystems Plc 4 D/655/3 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655A 2.2 CMX655D 3 Pin List 3.1 CMX655A 3.2 CMX655D 4 External Components 4.1 CMX655A 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 4.2 CMX655D 4.2.1 Power Supply and Pin Decoupling 4.2.2 SPI 4.2.3 TWI 4.2.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.4.2 Analogue Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Automatic Gain Control 5.6.2.1 AGC Registers 5.6.3 Noise Gate 5.6.3.1 Noise Gate Registers 5.6.4 Record Level Detection 5.6.4.1 Record Level Detection Registers 5.6.5 Playback Preamplifier Gain 5.6.5.1 Playback Preamplifier Gain Register 5.6.6 Playback Volume Control 5.6.6.1 Playback Volume Register 5.6.7 Automatic Level Control 5.6.7.1 ALC Registers 5.6.8 Digital Sidetone 5.6.8.1 Digital Sidetone Register 5.6.9 Voice Filters 5.6.9.1 Low Pass Filter 5.6.9.2 DC Blocking Filter 5.6.9.3 High Pass Filter 5.6.9.4 Voice Filters Registers 5.6.10 Channel Multiplexing 5.6.11 Click-and-Pop Reduction 5.6.11.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 DC-offset Calibration 6.1.3 Configuration 6.1.4 Enable Audio Channels 6.1.5 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D/CMX655A End of Document
6 Application Notes ... 57
6.1 Programming Examples ... 57 6.1.1 Start-up ... 57 6.1.2 DC-offset Calibration ... 57 6.1.3 Configuration ... 58 6.1.4 Enable Audio Channels .. 58 6.1.5 Shutdown .. 58
7 Performance Specification .. 59
7.1 Electrical Performance .. 59 7.1.1 Absolute Maximum Ratings .. 59 7.1.2 Operating Limits .. 59 7.1.3 Operating Characteristics .. 60 7.2 Typical Performance Characteristics ... 68 7.2.1 THD+N vs. Level performance ... 68 7.2.2 THD+N vs. Frequency performance ... 71 7.2.3 Class D Amplifier Efficiency ... 73 7.2.4 Filter Performance Speaker Channel ... 74 7.2.5 Filter Performance Microphone Channel .. 76 7.3 Packaging... 78 7.3.1 CMX655D/CMX655A ... 78 Table Page Table 1 CMX655A Pin List by Number ... 8 Table 2 CMX655A Pin List by Group .. 9 Table 3 CMX655D Pin List by Number ... 11 Table 4 CMX655D Pin List by Group .. 12 Table 5 CMX655A Component Values ... 14 Table 6 CMX655A SPI Component Values ... 15 Table 7 CMX655A TWI Component Values .. 16 Table 8 CMX655A AC Coupling Component Values ... 17 Table 9 CMX655D Component Values ... 18 Table 10 CMX655D SPI Component Value ... 19 Table 11 CMX655D TWI Component Values .. 20 Table 12 External Supply Voltages ... 22 Table 13 Supply and POR Threshold Voltages ... 22 Table 14 Bypass Mode Component Values.. 28 Table 15 CMX655D/CMX655A Slave Addresses .. 45 Table 16 Register Address Map ... 55 Table 17 SPI Timing Parameter Values .. 64 Table 18 TWI Standard Mode Timing Parameters ... 65 Table 19 TWI Fast Mode Timing Parameters ... 66 Table 20 TWI Pull-up Resistors and Bus Capacitance .. 66 Table 21 SAI Timing Parameters .. 67 Table 22 Digital Microphone Timing Parameters .. 67 Figure Page Figure 1 CMX655A Simplified Block Diagram... 1 Figure 2 CMX655D Simplified Block Diagram .. 1 Figure 3 CMX655A Block Diagram ... 7 Figure 4 CMX655D Block Diagram ... 7 Figure 5 CMX655A Pin Arrangement ... 10 Figure 6 CMX655D Pin Arrangement ... 13 Figure 7 CMX655A Power Supply and Pin Decoupling ... 14 Figure 8 CMX655A SPI Connections ... 15 2018 CML Microsystems Plc 4 D/655/3 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655A 2.2 CMX655D 3 Pin List 3.1 CMX655A 3.2 CMX655D 4 External Components 4.1 CMX655A 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 4.2 CMX655D 4.2.1 Power Supply and Pin Decoupling 4.2.2 SPI 4.2.3 TWI 4.2.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.4.2 Analogue Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Automatic Gain Control 5.6.2.1 AGC Registers 5.6.3 Noise Gate 5.6.3.1 Noise Gate Registers 5.6.4 Record Level Detection 5.6.4.1 Record Level Detection Registers 5.6.5 Playback Preamplifier Gain 5.6.5.1 Playback Preamplifier Gain Register 5.6.6 Playback Volume Control 5.6.6.1 Playback Volume Register 5.6.7 Automatic Level Control 5.6.7.1 ALC Registers 5.6.8 Digital Sidetone 5.6.8.1 Digital Sidetone Register 5.6.9 Voice Filters 5.6.9.1 Low Pass Filter 5.6.9.2 DC Blocking Filter 5.6.9.3 High Pass Filter 5.6.9.4 Voice Filters Registers 5.6.10 Channel Multiplexing 5.6.11 Click-and-Pop Reduction 5.6.11.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 DC-offset Calibration 6.1.3 Configuration 6.1.4 Enable Audio Channels 6.1.5 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D/CMX655A End of Document
