Datasheet CMX655A, CMX655D (CML Microcircuits) - 5

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Ultra-Low Power Voice Codec CMX655D/CMX655A Figure 9 CMX655A TWI Connections ... 16 Figure 10 CMX655A Speaker and Microphone Connections ... 17 Figure 11 CMX655D Power Supply and Pin Decoupling .. 18 Figure 12 CMX655D SPI Connections... 19 Figure 13 CMX655D TWI Connections ... 20 Figure 14 CMX655D Speaker and Microphone Connections ... 21 Figure 15 Main Clock Generation .. 23 Figure 16 Integer-N PLL ... 24 Figure 17 PLL Loop Filter .. 24 Figure 18 CMX655D Digital Microphone Interface .. 27 Figure 19 CMX655A Analogue Microphone Interface ... 27 Figure 20 External Microphone Connections for Bypass Mode ... 28 Figure 21 Audio signal processing block diagram with gain level block highlighted .. 29 Figure 22 Microphone interface and Audio signal processing block diagrams, showing AGC control blocks highlighted .. 30 Figure 23 Audio signal processing block diagram with Noise Gate block highlighted ... 32 Figure 24 Noise Gate Response ... 33 Figure 25 Audio signal processing block diagram with Level Detect block highlighted ... 35 Figure 26 Audio signal processing block diagram with preamp block highlighted .. 36 Figure 27 Audio signal processing block diagram with the volume block highlighted ... 37 Figure 28 Audio signal processing block diagram with ALC block highlighted ... 38 Figure 29 ALC Response ... 38 Figure 30 Audio signal processing block diagram with the Digital Side Tone path and block highlighted ... 40 Figure 31 Audio signal processing block diagram with Voice Filter blocks highlighted ... 41 Figure 32 Low Pass Filter Frequency Response ... 41 Figure 33 High Pass Filter Frequency Response ... 42 Figure 34 Audio signal processing block diagram with Mic Mux and Amp Mux block highlighted ... 43 Figure 35 SPI Write Transfer .. 44 Figure 36 SPI Read Transfer ... 44 Figure 37 SPI N-Byte Write Transfer .. 45 Figure 38 SPI N-Byte Read Transfer ... 45 Figure 39 TWI Write Transfer .. 46 Figure 40 TWI Read Transfer Address Phase ... 46 Figure 41 TWI Read Transfer Data Phase... 47 Figure 42 TWI Interrupt Status Register Read Transfer ... 47 Figure 43 TWI N-Byte Write Transfer .. 47 Figure 44 TWI N-Byte Read Transfer.. 47 Figure 45 I2S Mode Data Transfer ... 48 Figure 46 Left-Justified Mode Data Transfer ... 49 Figure 47 PCM Mode Dual-channel Data Transfer .. 49 Figure 48 PCM Mode Single-channel Data Transfer .. 50 Figure 49 PCM Slave Mode Dual-channel Companded Data Transfer ... 50 Figure 50 SPI Timing Diagram .. 64 Figure 51 TWI Timing Diagram .. 65 Figure 52 SAI Timing Diagram .. 67 Figure 53 Digital Microphone Timing Diagram .. 67 Figure 54 Class D amplifier THD+N vs. Level 48ksps .. 68 Figure 55 Class D amplifier THD+N vs. Level 32ksps .. 68 Figure 56 Class D amplifier THD+N vs. Level 16ksps .. 69 Figure 57 Class D amplifier THD+N vs. Level 8ksps .. 69 Figure 58 Line out amplifier THD+N vs. Level 48/32/16/8ksps .. 70 Figure 59 Class D amplifier THD+N vs. Frequency 48ksps ... 71 Figure 60 Class D amplifier THD+N vs. Frequency 32ksps ... 71 Figure 61 Class D amplifier THD+N vs. Frequency 16ksps ... 72 Figure 62 Class D amplifier THD+N vs. Frequency 8ksps ... 72 Figure 63 Line out amplifier THD+N vs. Frequency 48/32/16/8ksps ... 73 Figure 64 Class D amplifier efficiency 4Ω ... 73 Figure 65 Class D Amplifier Efficiency 8Ω .. 74 Figure 66 Low Pass Filter Response Speaker Channel ... 74 Figure 67 High Pass Filter Response Speaker Channel ... 75 Figure 68 Low Pass Filter response Microphone Channels .. 76 Figure 69 High Pass Filter Response Microphone Channels .. 77 Figure 70 VQFN-24 Mechanical Outline (Q6)... 78  2018 CML Microsystems Plc 5 D/655/3 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655A 2.2 CMX655D 3 Pin List 3.1 CMX655A 3.2 CMX655D 4 External Components 4.1 CMX655A 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 4.2 CMX655D 4.2.1 Power Supply and Pin Decoupling 4.2.2 SPI 4.2.3 TWI 4.2.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.4.2 Analogue Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Automatic Gain Control 5.6.2.1 AGC Registers 5.6.3 Noise Gate 5.6.3.1 Noise Gate Registers 5.6.4 Record Level Detection 5.6.4.1 Record Level Detection Registers 5.6.5 Playback Preamplifier Gain 5.6.5.1 Playback Preamplifier Gain Register 5.6.6 Playback Volume Control 5.6.6.1 Playback Volume Register 5.6.7 Automatic Level Control 5.6.7.1 ALC Registers 5.6.8 Digital Sidetone 5.6.8.1 Digital Sidetone Register 5.6.9 Voice Filters 5.6.9.1 Low Pass Filter 5.6.9.2 DC Blocking Filter 5.6.9.3 High Pass Filter 5.6.9.4 Voice Filters Registers 5.6.10 Channel Multiplexing 5.6.11 Click-and-Pop Reduction 5.6.11.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 DC-offset Calibration 6.1.3 Configuration 6.1.4 Enable Audio Channels 6.1.5 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D/CMX655A End of Document