Datasheet LTC6957-1, LTC6957-2, LTC6957-3, LTC6957-4 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter |
| Pages / Page | 38 / 9 — ELECTRICAL CHARACTERISTICS LTC6957-3/LTC6957-4. The |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
ELECTRICAL CHARACTERISTICS LTC6957-3/LTC6957-4. The
Model Line for this Datasheet
- LTC6957HMS-1#PBF LTC6957HMS-1#TRPBF LTC6957HMS-2#PBF LTC6957HMS-2#TRPBF LTC6957HMS-3#PBF LTC6957HMS-3#TRPBF LTC6957HMS-4#PBF LTC6957HMS-4#TRPBF LTC6957IDD-1#PBF LTC6957IDD-1#TRPBF LTC6957IDD-2#PBF LTC6957IDD-2#TRPBF LTC6957IDD-3#PBF LTC6957IDD-3#TRPBF LTC6957IDD-4#PBF LTC6957IDD-4#TRPBF LTC6957IMS-1#PBF LTC6957IMS-1#TRPBF LTC6957IMS-2#PBF LTC6957IMS-2#TRPBF LTC6957IMS-3#PBF LTC6957IMS-3#TRPBF LTC6957IMS-4#PBF LTC6957IMS-4#TRPBF
Text Version of Document
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS LTC6957-3/LTC6957-4 The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD/2, unless otherwise specified. All voltages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Logic Inputs
VIH High Level SD or Filt Input Voltage l V+ – 0.4 V VIL Low Level SD or Filt Input Voltage l 0.4 V IIN_DIG Input Current SD or Filt Pins l 0.1 ±10 µA
Additive Phase Noise and Jitter
fIN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L) 10Hz Offset –123 dBc/Hz 100Hz Offset –133 dBc/Hz 1kHz Offset –143 dBc/Hz 10kHz Offset –152 dBc/Hz 100kHz Offset –156 dBc/Hz >1MHz Offset –156 dBc/Hz Jitter (10Hz to 150MHz) 146 fsRMS Jitter (12kHz to 20MHz) 53 fsRMS fIN = 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L) 10Hz Offset –132 dBc/Hz 100Hz Offset –142 dBc/Hz 1kHz Offset –150.6 dBc/Hz 10kHz Offset –156.5 dBc/Hz 100kHz Offset –157.4 dBc/Hz >1MHz Offset –157.4 dBc/Hz Jitter (10Hz to 61.44MHz) 192 fsRMS Jitter (12kHz to 20MHz) 109 fsRMS fIN = 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L) 10Hz Offset –135 dBc/Hz 100Hz Offset –145 dBc/Hz 1kHz Offset –153 dBc/Hz 10kHz Offset –159.8 dBc/Hz 100kHz Offset –161 dBc/Hz >1MHz Offset –161 dBc/Hz Jitter (10Hz to 50MHz) 142 fsRMS Jitter (12kHz to 20MHz) 90 fsRMS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings only at the maximum operating supply voltage of 3.45V; 10mA of input may cause permanent damage to the device. Exposure to any Absolute current with the absolute maximum supply voltage of 3.6V may create Maximum Rating condition for extended periods may affect device permanent damage from voltage stress. reliability and lifetime.
Note 3:
With 3.6V Absolute Maximum supply voltage, the LTC6957-3/
Note 2:
Input pins IN+, IN–, FILTA, FILTB, SD1 and SD2 are protected by LTC6957-4 CMOS outputs can sink 30mA while low, and source 30mA steering diodes to either supply. If the inputs go beyond either supply rail, while high without damage. However, if overdriven or subject to an the input current should be limited to less than 10mA. If pushing current inductive load kick outside the supply rails, 30mA can create damaging into FILTB, the Pin 6 voltage must be limited to 4V. On the logic pins voltage stress and is not guaranteed unless VDD is limited to 3.15V. (FILTA, FILTB, SD1 and SD2) the Absolute Maximum input current applies 6957fb For more information www.linear.com/LTC6957-1 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
ELECTRICAL CHARACTERISTICS LTC6957-3/LTC6957-4 The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD/2, unless otherwise specified. All voltages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Logic Inputs
VIH High Level SD or Filt Input Voltage l V+ – 0.4 V VIL Low Level SD or Filt Input Voltage l 0.4 V IIN_DIG Input Current SD or Filt Pins l 0.1 ±10 µA
Additive Phase Noise and Jitter
fIN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L) 10Hz Offset –123 dBc/Hz 100Hz Offset –133 dBc/Hz 1kHz Offset –143 dBc/Hz 10kHz Offset –152 dBc/Hz 100kHz Offset –156 dBc/Hz >1MHz Offset –156 dBc/Hz Jitter (10Hz to 150MHz) 146 fsRMS Jitter (12kHz to 20MHz) 53 fsRMS fIN = 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L) 10Hz Offset –132 dBc/Hz 100Hz Offset –142 dBc/Hz 1kHz Offset –150.6 dBc/Hz 10kHz Offset –156.5 dBc/Hz 100kHz Offset –157.4 dBc/Hz >1MHz Offset –157.4 dBc/Hz Jitter (10Hz to 61.44MHz) 192 fsRMS Jitter (12kHz to 20MHz) 109 fsRMS fIN = 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L) 10Hz Offset –135 dBc/Hz 100Hz Offset –145 dBc/Hz 1kHz Offset –153 dBc/Hz 10kHz Offset –159.8 dBc/Hz 100kHz Offset –161 dBc/Hz >1MHz Offset –161 dBc/Hz Jitter (10Hz to 50MHz) 142 fsRMS Jitter (12kHz to 20MHz) 90 fsRMS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings only at the maximum operating supply voltage of 3.45V; 10mA of input may cause permanent damage to the device. Exposure to any Absolute current with the absolute maximum supply voltage of 3.6V may create Maximum Rating condition for extended periods may affect device permanent damage from voltage stress. reliability and lifetime.
Note 3:
With 3.6V Absolute Maximum supply voltage, the LTC6957-3/
Note 2:
Input pins IN+, IN–, FILTA, FILTB, SD1 and SD2 are protected by LTC6957-4 CMOS outputs can sink 30mA while low, and source 30mA steering diodes to either supply. If the inputs go beyond either supply rail, while high without damage. However, if overdriven or subject to an the input current should be limited to less than 10mA. If pushing current inductive load kick outside the supply rails, 30mA can create damaging into FILTB, the Pin 6 voltage must be limited to 4V. On the logic pins voltage stress and is not guaranteed unless VDD is limited to 3.15V. (FILTA, FILTB, SD1 and SD2) the Absolute Maximum input current applies 6957fb For more information www.linear.com/LTC6957-1 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
