Datasheet ADSP-SC570, ADSP-SC571, ADSP-SC572, ADSP-SC573, ADSP-21571, ADSP-21573 (Analog Devices) - 4

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Table 2. Comparison of ADSP-SC57x/ADSP-2157x Processor Features1 ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- Processor Feature SC570 SC571 SC572 SC573 21571 21573
ARM Cortex-A5 (MHz, Max) 450 500 450 500 N/A N/A ARM Core L1 Cache (I, D kB) 32, 32 32, 32 32, 32 32, 32 N/A N/A ARM Core L2 Cache (kB) 256 256 256 256 N/A N/A SHARC+ Core1 (MHz, Max) 450 500 450 500 500 500 SHARC+ Core2 (MHz, Max) N/A 500 N/A 500 500 500 SHARC L1 SRAM (kB) 1 × 384 2 × 384 1 × 384 2 × 384 2 × 384 2 × 384 m ry L2 SRAM (Shared) (MB) 1 1 1 1 1 1 o te m DDR3/DDR2/LPDDR1 Controller Sys N/A N/A 1 1 N/A 1 Me (16-bit) USB 2.0 HS + PHY (Host/Device/OTG) N/A N/A 1 1 N/A N/A EMAC Std/AVB + Timer IEEE 1588 10/100 10/100 10/100/1000 10/100/1000 N/A N/A SDIO/eMMC N/A N/A 1 1 N/A N/A Link Ports 1 1 2 2 1 2 GPIO Ports Port A to D Port A to D Port A to F Port A to F Port A to D Port A to F GPIO + DAI Pins 64 + 20 64 + 20 92 + 20 92 + 20 64 + 20 92 + 20 Package Options 176-LQFP 176-LQFP 400-BGA 400-BGA 176-LQFP 400-BGA 1 N/A means not applicable.
Table 3. Comparison of ADSP-SC57x/ADSP-2157x Processor Features for Automotive 1 ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- Processor Feature SC570W SC571W SC572W SC573W 21571W 21573W
ARM Cortex-A5 (MHz, Max) 450 500 450 500 N/A N/A ARM Core L1 Cache (I, D kB) 32, 32 32, 32 32, 32 32, 32 N/A N/A ARM Core L2 Cache (kB) 256 256 256 256 N/A N/A SHARC+ Core1 (MHz, Max) 450 500 450 500 500 500 SHARC+ Core2 (MHz, Max) N/A 500 N/A 500 500 500 SHARC L1 SRAM (kB) 1 × 384 2 × 384 1 × 384 2 × 384 2 × 384 2 × 384 m ry L2 SRAM (Shared) (MB) 1 1 1 1 1 1 o te m DDR3/DDR2/LPDDR1 Controller Sys N/A N/A 1 1 N/A 1 Me (16-bit) USB 2.0 HS + PHY (Host/Device/OTG) N/A N/A 1 1 N/A N/A EMAC Std/AVB + Timer IEEE 1588 10/100 10/100 10/100/1000 10/100/1000 N/A N/A SDIO/eMMC N/A N/A 1 1 N/A N/A MLB 3-Pin/6-Pin 3-pin 3-pin 6-pin/3-pin 6-pin/3-pin 3-pin 6-pin/3-pin Link Ports 1 1 2 2 1 2 GPIO Ports Port A to D Port A to D Port A to F Port A to F Port A to D Port A to F GPIO + DAI Pins 64 + 20 64 + 20 92 + 20 92 + 20 64 + 20 92 + 20 Package Options 176-LQFP 176-LQFP 400-BGA 400-BGA 176-LQFP 400-BGA 1 N/A means not applicable. Rev. B | Page 4 of 142 | June 2018 Document Outline System Features Memory Additional Features Table Of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC57x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC57x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features ARM TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Parity Protected ARM L1 Cache Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Port (LP) ADC Control Module (ACM) Interface Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller (BGA Only) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages (BSPs) for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 176-Lead LQFP Signal Descriptions GPIO Multiplexing for 176-Lead LQFP Package ADSP-SC57x/ADSP-2157x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAI0 Pin to DAI0 Pin Direct Routing Up/Down Counter/Rotary Encoder Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) 10/100 EMAC Timing 10/100/1000 EMAC Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 176-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide