Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 (Analog Devices) - 5

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ADSP-21362/ADSP-21363/ADSP-2 1364/ADSP-21365/ADSP-21366 Data Register File
processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow Each processing element contains a general-purpose data regis- the creation of up to 32 circular buffers (16 primary register sets, ter file. The register files transfer data between the computation 16 secondary). The DAGs automatically handle address pointer units and the data buses, and store intermediate results. These wraparound, reduce overhead, increase performance, and sim- 10-port, 32-register (16 primary, 16 secondary) files, combined plify implementation. Circular buffers can start and end at any with the ADSP-2136x enhanced Harvard architecture, allow memory location. unconstrained data flow between computation units and inter- nal memory. The registers in PEX are referred to as R0–R15 and
Flexible Instruction Set
in PEY as S0–S15. The 48-bit instruction word accommodates a variety of parallel
Context Switch
operations for concise programming. For example, the processor can conditionally execute a multiply, an add, and a Many of the processor’s registers have secondary registers that subtract in both processing elements while branching and fetch- can be activated during interrupt servicing for a fast context ing up to four 32-bit values from memory—all in a single switch. The data registers in the register file, the DAG registers, instruction. and the multiplier result register all have secondary registers. The primary registers are active at reset, while the secondary
On-Chip Memory
registers are activated by control bits in a mode control register. The processor contains 3M bits of internal SRAM and 4M bits
Universal Registers
of internal ROM. Each block can be configured for different combinations of code and data storage (see Table 3). Each The universal registers are general purpose registers. The memory block supports single-cycle, independent accesses by USTAT (4) registers allow easy bit manipulations (Set, Clear, the core processor and I/O processor. The processor’s memory Toggle, Test, XOR) for all system registers (control/status) of architecture, in combination with its separate on-chip buses, the core. allows two data transfers from the core and one from the I/O The data bus exchange register (PX) permits data to be passed processor, in a single cycle. between the 64-bit PM data bus and the 64-bit DM data bus, or The SRAM can be configured as a maximum of 96K words of between the 40-bit register file and the PM/DM data bus. These 32-bit data, 192K words of 16-bit data, 64K words of 48-bit registers contain hardware to handle the data width difference. instructions (or 40-bit data), or combinations of different word
Timer
sizes up to 3M bits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage A core timer that can generate periodic software interrupts. The format is supported that effectively doubles the amount of data core timer can be configured to use FLAG3 as a timer expired that can be stored on-chip. Conversion between the 32-bit signal. floating-point and 16-bit floating-point formats is performed in
Single-Cycle Fetch of Instruction and Four Operands
a single instruction. While each memory block can store combi- nations of code and data, accesses are most efficient when one The processor features an enhanced Harvard architecture in block stores data using the DM bus for transfers, and the other which the data memory (DM) bus transfers data and the pro- block stores instructions and data using the PM bus for gram memory (PM) bus transfers both instructions and data transfers. (see Figure 2). With the its separate program and data memory buses and on-chip instruction cache, the processor can simulta- Using the DM bus and PM buses, with one bus dedicated to neously fetch four operands (two over each data bus) and one each memory block, assures single-cycle execution with two instruction (from the cache), all in a single cycle. data transfers. In this case, the instruction must be available in the cache.
Instruction Cache On-Chip Memory Bandwidth
The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four The internal memory architecture allows three accesses at the data values. The cache is selective—only the instructions whose same time to any of the four blocks, assuming no block con- fetches conflict with PM bus data accesses are cached. This flicts. The total bandwidth is gained with DMD and PMD buses cache allows full-speed execution of core looped operations (2 × 64-bits, core CLK) and the IOD bus (32-bit, PCLK). such as digital filter multiply-accumulates, and FFT butterfly
ROM-Based Security
processing. The processor has a ROM security feature that provides hard-
Data Address Generators with Zero-Overhead Hardware
ware support for securing user software code by preventing
Circular Buffer Support
unauthorized reading from the internal code. When using this The processor’s two data address generators (DAGs) are used feature, the processor does not boot-load any external code, exe- for indirect addressing and implementing circular data buffers cuting exclusively from internal ROM. Additionally, the in hardware. Circular buffers allow efficient programming of processor is not freely accessible via the JTAG port. Instead, a delay lines and other data structures required in digital signal unique 64-bit key, which must be scanned in through the JTAG Rev. J | Page 5 of 60 | July 2013 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture Parallel Port Serial Peripheral (Compatible) Interface Pulse-Width Modulation Digital Audio Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Digital Transmission Content Protection (DTCP) Memory-to-Memory (MTM) Synchronous/Asynchronous Sample Rate Converter (SRC) Input Data Port (IDP) Precision Clock Generator (PCG) Peripheral Timers I/O Processor Features DMA Controller System Design Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin to Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 144-Lead LQFP_EP Pin Configurations 136-Ball BGA Pin Configurations Package Dimensions Surface-Mount Design Automotive Products Ordering Guide