Datasheet EFR32BG21 (Silicon Labs) - 9

EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet System Overview
3.5.3 Real Time Clock with Capture (RTCC)
The Real Time Clock with Capture (RTCC) is a 32-bit counter providing timekeeping down to EM3. The RTCC can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals. A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli- cation software.
3.5.4 Back-Up Real Time Counter
The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined inver- vals.
3.5.5 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can also monitor autonomous systems driven by the Peripheral Reflex System (PRS).
3.6 Communications and Other Digital Peripherals 3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup- porting: • ISO7816 SmartCards • IrDA • I2S
3.6.2 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans- fers. Automatic recognition of slave addresses is provided in active and low energy modes. Note that not all instances of I2C are avalia- ble in all energy modes.
3.6.3 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement. Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph- erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving pow- er.
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| Building a more connected world. Rev. 1.0 | 9 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Radio 3.2.1 Antenna Interface 3.2.2 Fractional-N Frequency Synthesizer 3.2.3 Receiver Architecture 3.2.4 Transmitter Architecture 3.2.5 Packet and State Trace 3.2.6 Data Buffering 3.2.7 Radio Controller (RAC) 3.3 General Purpose Input/Output (GPIO) 3.4 Clocking 3.4.1 Clock Management Unit (CMU) 3.4.2 Internal and External Oscillators 3.5 Counters/Timers and PWM 3.5.1 Timer/Counter (TIMER) 3.5.2 Low Energy Timer (LETIMER) 3.5.3 Real Time Clock with Capture (RTCC) 3.5.4 Back-Up Real Time Counter 3.5.5 Watchdog Timer (WDOG) 3.6 Communications and Other Digital Peripherals 3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 3.6.2 Inter-Integrated Circuit Interface (I2C) 3.6.3 Peripheral Reflex System (PRS) 3.7 Security Features 3.7.1 Standard Security 3.7.2 True Random Number Generator 3.8 Analog 3.8.1 Analog Comparator (ACMP) 3.8.2 Analog to Digital Converter (ADC) 3.9 Reset Management Unit (RMU) 3.10 Core and Memory 3.10.1 Processor Core 3.10.2 Memory System Controller (MSC) 3.10.3 Linked Direct Memory Access Controller (LDMA) 3.11 Memory Map 3.12 Configuration Summary 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Absolute Maximum Ratings 4.1.2 General Operating Conditions 4.1.3 Thermal Characteristics 4.1.4 Current Consumption 4.1.4.1 MCU current consumption at 1.8V 4.1.4.2 MCU current consumption at 3.0V 4.1.4.3 Radio current consumption at 1.8V 4.1.4.4 Radio current consumption at 3.0V 4.1.5 2.4 GHz RF Transceiver Characteristics 4.1.5.1 RF Transmitter Characteristics 4.1.5.2 RF Receiver Characteristics 4.1.6 Flash Characteristics 4.1.7 Wake Up, Entry, and Exit times 4.1.8 Oscillators 4.1.8.1 High Frequency Crystal Oscillator 4.1.8.2 Low Frequency Crystal Oscillator 4.1.8.3 High Frequency RC Oscillator (HFRCO) 4.1.8.4 Fast Start_Up RC Oscillator (FSRCO) 4.1.8.5 Low Frequency RC Oscillator 4.1.8.6 Ultra Low Frequency RC Oscillator 4.1.9 GPIO Pins (3V GPIO pins) 4.1.10 Analog to Digital Converter (ADC) 4.1.11 Analog Comparator (ACMP) 4.1.12 Temperature Sense 4.1.13 Brown Out Detectors 4.1.13.1 DVDD BOD 4.1.13.2 LE DVDD BOD 4.1.13.3 AVDD and VIO BODs 4.1.14 SPI Electrical Specifications 4.1.14.1 SPI Master Timing 4.1.14.2 SPI Slave Timing 4.1.15 I2C Electrical Specifications 4.1.15.1 I2C Standard-mode (Sm) 4.1.15.2 I2C Fast-mode (Fm) 4.1.15.3 I2C Fast-mode Plus (Fm+) 4.2 Typical Performance Curves 4.2.1 Supply Current 4.2.2 2.4 GHz Radio 5. Typical Connection Diagrams 5.1 Power 5.2 RF Matching Networks 5.2.1 2.4 GHz 0 dBm Matching Network 5.2.2 2.4 GHz 10 dBm Matching Network 5.2.3 2.4 GHz 20 dBm Matching Network 5.3 Other Connections 6. Pin Definitions 6.1 QFN32 2.4GHz Device Pinout 6.2 Alternate Function Table 6.3 Analog Peripheral Connectivity 6.4 Digital Peripheral Connectivity 7. QFN32 Package Specifications 7.1 QFN32 Package Dimensions 7.2 QFN32 PCB Land Pattern 7.3 QFN32 Package Marking 8. Revision History