Datasheet S-35720 (ABLIC) - 9

WAKE-UP TIMER IC PIN-SELECTABLE WAKE-UP TIMER IC
Rev.1.0_00
S-35720 Series INT Pin Interrupt Signal Output
_______ _______ The RST pin of the S-35720 Series has a built-in chattering elimination circuit. Therefore, after the RST pin changes from "L" to "H", a delay occurs until the timer starts the count-up action. Furthermore, an internal circuit delay occurs until _______ the first interrupt signal occurs. Since the maximum delay time after the RST pin changes from "L" to "H" is approximately 700 ms, the timing for the occurrence of the first interrupt signal is delayed. _______ After the RST pin changes from "L" to "H", the S-35720 Series takes the values set to the SET0 pin and the SET1 pin. As a result, even if the SET0 pin and the SET1 pin settings are changed during timer count-up action, the interrupt time does not change.
1. One-shot loop time-out
One-shot loop time-out is a type to output the "L" pulse interrupt signal repeatedly from the INT pin. _______ After the RST pin changes from "L" to "H", the timer starts the operation. Then, the INT pin outputs "L" pulse when the timer value matches the value set to the SET0 pin and the SET1 pin
*1
. After that, the S-35720 Series resets the timer automatically, and restarts a count-up action. _______ If "L" is input to the RST pin before the timer value matches the value set to the SET0 pin and the SET1 pin
*1
, the timer is reset.
*1.
4 types of interrupt time can be selected depending on the SET0 pin and the SET1 pin settings.
Remark
The above description is the example of S-35720C01I (Nch open-drain output). In S-35720C02I (CMOS output), the INT pin output is the inverse logic of S-35720C01I. Reset Reset RST Internal circuit delay Internal circuit delay One-shot loop time-out One-shot loop time-out One-shot loop time-out INT SET0 and SET1 pin settings 7.8 ms 7.8 ms SET0 and SET1 pin settings 7.8 ms take-in timing take-in timing After the reset is released, INT pin outputs "L" pulse periodically
Figure 7 Output Timing of One-shot Loop Time-out (S-35720C01I / Nch Open-drain Output)
Reset Reset RST Internal circuit delay Internal circuit delay One-shot loop time-out One-shot loop time-out One-shot loop time-out INT SET0 and SET1 pin settings 125 ms 125 ms SET0 and SET1 pin settings 125 ms take-in timing take-in timing After the reset is released, INT pin outputs "H" pulse periodically
Figure 8 Output Timing of One-shot Loop Time-out (S-35720C02I / CMOS Output)
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