Datasheet L5965 (STMicroelectronics) - 4
| Manufacturer | STMicroelectronics |
| Description | Multiple power management for automotive vision and radar systems |
| Pages / Page | 85 / 4 — L5965. Pins description. Figure 3. Pin out (top view). Table 1. Pin … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
L5965. Pins description. Figure 3. Pin out (top view). Table 1. Pin description and functions. No. Pin name. Pin type. Description
Model Line for this Datasheet
Text Version of Document
L5965 Pins description 2 Pins description Figure 3. Pin out (top view)
T VSLDO LDO AGND SGND DGND FAUL RESET_B DO CLK DI CSN WDI 48 47 46 45 44 43 42 41 40 39 38 37 REF 1 36 SYNCOUT VBAT1 2 35 SYNCIN 3 EXTSUP 34 BST2 VREG 4 33 VBAT2 BST1 5 32 PH2 GH1 6 31 PGND2 PH1 7 30 VREG2_S GL1 8 29 COMP2 PGND1 9 28 VBOOST_S sensep 10 27 PGND5 sensen 11 26 PH5 COMP1 12 25 WKUP 13 14 15 16 17 18 19 20 21 22 23 24 PH3 PH4 BST3 VIN3 VIN4 BST4 Debug PGND3 PGND4 VREG1_S VREG3_S VREG4_S GAPG2206151609PS
Table 1. Pin description and functions No. Pin name Pin type Description
1 REF O Accurate reference voltage output 2 VBAT1 S VBAT1 for inner reference and supply for pre-BUCK1 external HS MOS 3 EXTSUP S Optional LV input for BUCK1, BUCK3, BUCK4 gate driver supply 4 VREG O Internal regulator for BUCK1, BUCK3, BUCK4 gate driver supply (decoupling) 5 BST1 I/O Boot-strap capacitor to supply BUCK1 high-side MOS gate-driver circuitry 6 GH1 O Gate driver of external high-side MOS 7 PH1 O Switching node BUCK1 8 GL1 O Gate driver of external low-side MOS 9 PGND1 G Ground for external low-side MOS driver circuitry 10 sensep I Positive differential current sense input for BUCK1 11 sensen I Negative differential current sense input for BUCK1 12 COMP1 I/O BUCK1 Error Amplifier compensation network 13 VREG1_S I BUCK1 regulated voltage output (to internal voltage monitors) 14 Debug I Device debug. Keep floating or connect to ground when not used
DS12567
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Rev 2 page 4/85
Document Outline 1 Overview 1.1 Simplified block diagram 1.2 Functional block diagram 2 Pins description 3 Electrical specifications 3.1 Absolute maximum ratings & operating voltage 3.2 Thermal data 3.2.1 Thermal resistance 3.2.2 Thermal warning and protection 3.3 Electrical characteristics 3.3.1 Electrical characteristic curves 4 Functional description 4.1 Programming by OTP 4.2 Voltage regulators and features description 4.2.1 VREG 4.2.2 Pre regulator BUCK1 4.2.3 Pre regulator BUCK2 4.2.4 Post regulator BUCK3 4.2.5 Post regulator BUCK4 4.2.6 BOOST 4.2.7 LDO 4.2.8 VREF 4.2.9 ADC 4.2.10 Wake up pin (WKUP) 4.2.11 Synchronizing pin (SYNC in/out) 4.2.12 Reset and Fault 4.2.13 Configurable watchdog and reset 4.2.14 Under-Voltage, Over-Voltage and Power-Good 4.2.15 Temperature control and VBATx voltage through internal ADC 4.2.16 Maximum Duty Cycle and Refresh Mode for Buck 4.2.17 Frequency-Hopping Spread Spectrum 5 SPI format and register mapping 5.1 SPI frame CRC generator 5.2 SPI registers mapping 5.2.1 SPI REG BUCK1 5.2.2 SPI REG BUCK2 5.2.3 SPI REG WD_REC_EN 5.2.4 SPI REG BUCK4 5.2.5 SPI REG BOOST VREF 5.2.6 SPI REG BUCK EN 5.2.7 SPI REG WD 5.2.8 SPI REG BUCK STAT1 5.2.9 SPI REG BUCK STAT2 5.2.10 SPI REG Fault Table PWUP 5.2.11 SPI REG ADC TH1 5.2.12 SPI REG ADC TH2 5.2.13 SPI REG ADC TH3 5.2.14 SPI REG ADC TH4 5.2.15 SPI REG ADC TH5 5.2.16 SPI REG ADC TH6 5.2.17 SPI REG ADC TH7 5.2.18 SPI REG ADC VBAT1 5.2.19 SPI REG ADC VBAT2 5.2.20 SPI REG OT Warning 5.2.21 SPI Fault STAT 5.2.22 SPI Silicon Version 5.2.23 SPI Device Identification 6 Device operating mode 6.1 Shutdown mode 6.2 Standby mode 6.3 INIT mode 6.4 REC mode 6.5 RAMPUP MAIN and SEC_UP 6.6 ACTIVE mode 6.7 OTP program mode 6.8 OTP bit mapping and register configuration 6.9 OTP (SAF) registers 6.9.1 SAF_REG_OP 6.9.2 SAF_REG_CFG 6.9.3 SAF_REG_DI 6.9.4 SAF_REG_D0_Bit_Ts 6.9.5 SAF_REG_STAT 6.10 Power down phase 6.11 Power up programming 7 Functional safety requirements 7.1 Functions and safety mechanism related to safety requirements 7.2 System safety mechanism 8 Application information 8.1 External components calculation 8.1.1 BUCK1 controller 8.1.1.1 RSENSE 8.1.1.2 BUCK1 output inductor 8.1.1.3 BUCK1 output capacitor 8.1.1.4 BUCK1 bootstrap capacitor 8.1.1.5 BUCK1 compensation network 8.1.2 BUCK2 controller 8.1.2.1 BUCK2 output inductor 8.1.2.2 BUCK2 output capacitor 8.1.2.3 BUCK2 compensation network 8.1.3 BUCK3, BUCK4 8.1.3.1 Output inductor and capacitor 8.1.3.2 Bootstrap capacitor for BUCK3 and BUCK4 8.1.3.3 Input capacitor 8.1.4 BOOST 8.1.4.1 BOOST output inductor 8.1.4.2 BOOST output capacitor 8.1.4.3 BOOST compensation network 8.1.4.4 Output diode for the BOOST converter 8.1.4.5 Input capacitor selection 8.2 PCB Layout example (BUCK1 as main regulator) 9 Package information 9.1 VFQFPN-48 (7x7x1.0 mm - opt. D) package information 9.2 VFQFPN-48 (7x7x1.0) marking information Revision history
T VSLDO LDO AGND SGND DGND FAUL RESET_B DO CLK DI CSN WDI 48 47 46 45 44 43 42 41 40 39 38 37 REF 1 36 SYNCOUT VBAT1 2 35 SYNCIN 3 EXTSUP 34 BST2 VREG 4 33 VBAT2 BST1 5 32 PH2 GH1 6 31 PGND2 PH1 7 30 VREG2_S GL1 8 29 COMP2 PGND1 9 28 VBOOST_S sensep 10 27 PGND5 sensen 11 26 PH5 COMP1 12 25 WKUP 13 14 15 16 17 18 19 20 21 22 23 24 PH3 PH4 BST3 VIN3 VIN4 BST4 Debug PGND3 PGND4 VREG1_S VREG3_S VREG4_S GAPG2206151609PS
Table 1. Pin description and functions No. Pin name Pin type Description
1 REF O Accurate reference voltage output 2 VBAT1 S VBAT1 for inner reference and supply for pre-BUCK1 external HS MOS 3 EXTSUP S Optional LV input for BUCK1, BUCK3, BUCK4 gate driver supply 4 VREG O Internal regulator for BUCK1, BUCK3, BUCK4 gate driver supply (decoupling) 5 BST1 I/O Boot-strap capacitor to supply BUCK1 high-side MOS gate-driver circuitry 6 GH1 O Gate driver of external high-side MOS 7 PH1 O Switching node BUCK1 8 GL1 O Gate driver of external low-side MOS 9 PGND1 G Ground for external low-side MOS driver circuitry 10 sensep I Positive differential current sense input for BUCK1 11 sensen I Negative differential current sense input for BUCK1 12 COMP1 I/O BUCK1 Error Amplifier compensation network 13 VREG1_S I BUCK1 regulated voltage output (to internal voltage monitors) 14 Debug I Device debug. Keep floating or connect to ground when not used
DS12567
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Rev 2 page 4/85
Document Outline 1 Overview 1.1 Simplified block diagram 1.2 Functional block diagram 2 Pins description 3 Electrical specifications 3.1 Absolute maximum ratings & operating voltage 3.2 Thermal data 3.2.1 Thermal resistance 3.2.2 Thermal warning and protection 3.3 Electrical characteristics 3.3.1 Electrical characteristic curves 4 Functional description 4.1 Programming by OTP 4.2 Voltage regulators and features description 4.2.1 VREG 4.2.2 Pre regulator BUCK1 4.2.3 Pre regulator BUCK2 4.2.4 Post regulator BUCK3 4.2.5 Post regulator BUCK4 4.2.6 BOOST 4.2.7 LDO 4.2.8 VREF 4.2.9 ADC 4.2.10 Wake up pin (WKUP) 4.2.11 Synchronizing pin (SYNC in/out) 4.2.12 Reset and Fault 4.2.13 Configurable watchdog and reset 4.2.14 Under-Voltage, Over-Voltage and Power-Good 4.2.15 Temperature control and VBATx voltage through internal ADC 4.2.16 Maximum Duty Cycle and Refresh Mode for Buck 4.2.17 Frequency-Hopping Spread Spectrum 5 SPI format and register mapping 5.1 SPI frame CRC generator 5.2 SPI registers mapping 5.2.1 SPI REG BUCK1 5.2.2 SPI REG BUCK2 5.2.3 SPI REG WD_REC_EN 5.2.4 SPI REG BUCK4 5.2.5 SPI REG BOOST VREF 5.2.6 SPI REG BUCK EN 5.2.7 SPI REG WD 5.2.8 SPI REG BUCK STAT1 5.2.9 SPI REG BUCK STAT2 5.2.10 SPI REG Fault Table PWUP 5.2.11 SPI REG ADC TH1 5.2.12 SPI REG ADC TH2 5.2.13 SPI REG ADC TH3 5.2.14 SPI REG ADC TH4 5.2.15 SPI REG ADC TH5 5.2.16 SPI REG ADC TH6 5.2.17 SPI REG ADC TH7 5.2.18 SPI REG ADC VBAT1 5.2.19 SPI REG ADC VBAT2 5.2.20 SPI REG OT Warning 5.2.21 SPI Fault STAT 5.2.22 SPI Silicon Version 5.2.23 SPI Device Identification 6 Device operating mode 6.1 Shutdown mode 6.2 Standby mode 6.3 INIT mode 6.4 REC mode 6.5 RAMPUP MAIN and SEC_UP 6.6 ACTIVE mode 6.7 OTP program mode 6.8 OTP bit mapping and register configuration 6.9 OTP (SAF) registers 6.9.1 SAF_REG_OP 6.9.2 SAF_REG_CFG 6.9.3 SAF_REG_DI 6.9.4 SAF_REG_D0_Bit_Ts 6.9.5 SAF_REG_STAT 6.10 Power down phase 6.11 Power up programming 7 Functional safety requirements 7.1 Functions and safety mechanism related to safety requirements 7.2 System safety mechanism 8 Application information 8.1 External components calculation 8.1.1 BUCK1 controller 8.1.1.1 RSENSE 8.1.1.2 BUCK1 output inductor 8.1.1.3 BUCK1 output capacitor 8.1.1.4 BUCK1 bootstrap capacitor 8.1.1.5 BUCK1 compensation network 8.1.2 BUCK2 controller 8.1.2.1 BUCK2 output inductor 8.1.2.2 BUCK2 output capacitor 8.1.2.3 BUCK2 compensation network 8.1.3 BUCK3, BUCK4 8.1.3.1 Output inductor and capacitor 8.1.3.2 Bootstrap capacitor for BUCK3 and BUCK4 8.1.3.3 Input capacitor 8.1.4 BOOST 8.1.4.1 BOOST output inductor 8.1.4.2 BOOST output capacitor 8.1.4.3 BOOST compensation network 8.1.4.4 Output diode for the BOOST converter 8.1.4.5 Input capacitor selection 8.2 PCB Layout example (BUCK1 as main regulator) 9 Package information 9.1 VFQFPN-48 (7x7x1.0 mm - opt. D) package information 9.2 VFQFPN-48 (7x7x1.0) marking information Revision history
