Datasheet ALT80600 (Allegro) - 8

ManufacturerAllegro
DescriptionLED Driver with Pre-Emptive Boost for Ultra-High Dimming Ratio and Low Output Ripple
Pages / Page33 / 8 — LED Driver with Pre-Emptive Boost. ALT80600 for Ultra-High Dimming Ratio …
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LED Driver with Pre-Emptive Boost. ALT80600 for Ultra-High Dimming Ratio and Low Output Ripple

LED Driver with Pre-Emptive Boost ALT80600 for Ultra-High Dimming Ratio and Low Output Ripple

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LED Driver with Pre-Emptive Boost ALT80600 for Ultra-High Dimming Ratio and Low Output Ripple ELECTRICAL CHARACTERISTICS [1] (continued): Unless otherwise noted, specifications are valid at VIN = 16 V, TJ = 25°C, • indi- cates specifications guaranteed over the full operating temperature range with TJ = –40°C to 125°C, typical specifications are at TJ = 25°C Characteristics Symbol Test Conditions Min. Typ. Max. Unit LED CURRENT SINKS
LEDx Accuracy [4] ErrLED iISET = 120 µA (RISET = 8.33 kΩ), VAPWM = 0 V ● − 0.7 3 % LEDx Matching ΔLEDx iISET = 120 µA, VAPWM = 0 V ● − 0.8 2 % LEDx Regulation Voltage V Measured individually with all other LED pins LED tied to 1 V, iISET = 120 µA, VAPWM = 0 V ● 600 700 800 mV IISET to ILEDx Current Gain AISET iISET = 120 µA, VAPWM = 0 V ● 816 833 850 A/A ISET Pin Voltage VISET 0.97 1 1.03 V Allowable ISET Current iISET ● 20 − 144 µA Sensed from each LED pin to GND while its LED String Partial-Short-Detect VLEDSC current sink is in regulation; all other LED pins ● 4.5 5.2 6 V tied to 1 V Maximum time duration before all LED Soft-Start Ramp Up Time [2] tSSRU channels come into regulation, or OVP is 18 21.5 25 ms tripped, whichever comes first EN goes from High to Low; exceeding tEN(OFF) Enable Pin Shut Down Delay [2] tEN(OFF) results in IC shutdown; measured in terms of − 32768 − cycles switching cycles Minimum PWM Dimming On-Time tPWMH First and subsequent PWM pulses ● − 0.3 0.4 µs
GATE PIN
Gate Pin Sink current IGSINK VGS = VIN, no input OCP fault − −113 − µA Gate Pin Source current IGSOURCE VGS = VIN – 6 V, input OCP fault tripped − 6 − mA Gate Shutdown Delay When Over- Current Fault Is Tripped [2] tFAULTT VIN – VSENSE = 200 mV; monitored at FAULT pin − − 3 µs Gate Voltage V Measured between GATE and VIN when gate GS is fully on − −6.7 − V
VSENSE PIN
VSENSE Pin Sink Current iADJ ● 16 20 24 µA VSENSE Trip Point VSENSETRIP Measured between VIN and VSENSE, RADJ = 0 ● 88 100 110 mV
FAULT PIN
FAULT Pull Down Voltage VFAULT IFAULT = 1 mA − − 0.5 V FAULT Pin Leakage Current iFAULT-LKG VFAULT = 5 V − − 1 µA
THERMAL PROTECTION (TSD)
Thermal Shutdown Threshold [2] TSD Temperature rising 155 170 − °C Thermal Shutdown Hysteresis [2] TSDHYS − 20 − °C [1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization; not production tested. [3] Minimum VIN = 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to VIN = 4 V. [4] LED current is trimmed to cancel variations in both Gain and ISET voltage. Allegro MicroSystems, LLC 8 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Applications Package Selection Guide Absolute Maximum Ratings Thermal Characteristics Typical Application – SEPIC Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Functional Description Enabling the IC Powering Up: LED Detection Phase Powering Up: Boost Output Undervoltage Soft Start Function Frequency Selection Synchronization Loss of External Sync Signal Switching Frequency Dithering Clock Out Function LED Current Setting PWM Dimming Pre-Emptive Boost (PEB) Analog Dimming with APWM Pin Extending LED Dimming Ratio Analog Dimming with External Voltage VDD Shutdown Fault Detection and Protection LED String Partial-Short Detect Boost Switch Overcurrent Protection Input Overcurrent Protection and Disconnect Switch Setting the Current Sense Resistor Input UVLO Fault Protection During Operation Fault Recovery Mechanism Package Outline Drawing Appendix A: Design Example