Datasheet AD7124-4-EP (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference |
| Pages / Page | 17 / 7 — Enhanced Product. AD7124-4-EP. Parameter1 Min. Typ. Max. Unit. Test. … |
| File Format / Size | PDF / 247 Kb |
| Document Language | English |
Enhanced Product. AD7124-4-EP. Parameter1 Min. Typ. Max. Unit. Test. Conditions/Comments
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Enhanced Product AD7124-4-EP Parameter1 Min Typ Max Unit Test Conditions/Comments
EXCITATION CURRENT SOURCES (IOUT0/IOUT1) Available on any analog input pin Output Current 50/100/250/ μA 500/750/1000 Initial Tolerance ±4 % TA = 25°C Drift 50 ppm/°C Current Matching ±0.5 % Matching between IOUT0 and IOUT1, VOUT = 0 V Drift Matching2 5 30 ppm/°C Line Regulation (AVDD) 2 %/V AVDD = 3 V ± 5% Load Regulation 0.2 %/V Output Compliance2 AVSS − 0.05 AVDD − 0.37 V 50 μA/100 μA/250 μA/500 μA current sources, 2% accuracy AVSS − 0.05 AVDD − 0.48 V 750 μA and 1000 μA current sources, 2% accuracy BIAS VOLTAGE (VBIAS) GENERATOR Available on any analog input pin VBIAS AVSS + (AVDD − V AVSS)/2 VBIAS Generator Start-Up Time 6.7 μs/nF Dependent on the capacitance connected to AINx TEMPERATURE SENSOR Accuracy ±0.5 °C Sensitivity 13,584 Codes/°C LOW-SIDE POWER SWITCH On Resistance (RON) 7 10 Ω Allowable Current2 30 mA Continuous current BURNOUT CURRENTS AIN Current 0.5/2/4 μA Analog inputs must be buffered DIGITAL OUTPUTS (P1 AND P2) Output Voltage High, VOH AVDD − 0.6 V ISOURCE = 100 μA Low, VOL 0.4 V ISINK = 100 μA DIAGNOSTICS Power Supply Monitor Detect Level Analog Low Dropout Regulator (ALDO) 1.6 V AVDD − AVSS ≥ 2.7 V Digital LDO (DLDO) 1.55 V IOVDD ≥ 1.75 V Reference Detect Level 0.7 1 V REF_DET_ERR bit active if VREF < 0.7 V AINM/AINP Overvoltage Detect Level AVDD + 0.04 V AINM/AINP Undervoltage Detect Level AVSS − 0.04 V INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 614.4 − 5% 614.4 614.4 + 5% kHz Duty Cycle 50:50 % External Clock Frequency 2.4576 MHz Internal divide by 4 Duty Cycle Range 45:55 to 55:45 % LOGIC INPUTS2 Input Voltage Low, VINL 0.3 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V 0.35 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V 0.7 V 2.3 V ≤ IOVDD ≤ 3.6 V High, VINH 0.7 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V 0.65 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V 1.7 V 2.3 V ≤ IOVDD < 2.7 V 2 V 2.7 V ≤ IOVDD ≤ 3.6 V Hysteresis 0.2 0.6 V 1.65 V ≤ IOVDD ≤ 3.6 V Input Currents −1 +1 μA VIN = IOVDD or GND Input Capacitance 10 pF All digital inputs Rev. 0 | Page 7 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
Enhanced Product AD7124-4-EP Parameter1 Min Typ Max Unit Test Conditions/Comments
EXCITATION CURRENT SOURCES (IOUT0/IOUT1) Available on any analog input pin Output Current 50/100/250/ μA 500/750/1000 Initial Tolerance ±4 % TA = 25°C Drift 50 ppm/°C Current Matching ±0.5 % Matching between IOUT0 and IOUT1, VOUT = 0 V Drift Matching2 5 30 ppm/°C Line Regulation (AVDD) 2 %/V AVDD = 3 V ± 5% Load Regulation 0.2 %/V Output Compliance2 AVSS − 0.05 AVDD − 0.37 V 50 μA/100 μA/250 μA/500 μA current sources, 2% accuracy AVSS − 0.05 AVDD − 0.48 V 750 μA and 1000 μA current sources, 2% accuracy BIAS VOLTAGE (VBIAS) GENERATOR Available on any analog input pin VBIAS AVSS + (AVDD − V AVSS)/2 VBIAS Generator Start-Up Time 6.7 μs/nF Dependent on the capacitance connected to AINx TEMPERATURE SENSOR Accuracy ±0.5 °C Sensitivity 13,584 Codes/°C LOW-SIDE POWER SWITCH On Resistance (RON) 7 10 Ω Allowable Current2 30 mA Continuous current BURNOUT CURRENTS AIN Current 0.5/2/4 μA Analog inputs must be buffered DIGITAL OUTPUTS (P1 AND P2) Output Voltage High, VOH AVDD − 0.6 V ISOURCE = 100 μA Low, VOL 0.4 V ISINK = 100 μA DIAGNOSTICS Power Supply Monitor Detect Level Analog Low Dropout Regulator (ALDO) 1.6 V AVDD − AVSS ≥ 2.7 V Digital LDO (DLDO) 1.55 V IOVDD ≥ 1.75 V Reference Detect Level 0.7 1 V REF_DET_ERR bit active if VREF < 0.7 V AINM/AINP Overvoltage Detect Level AVDD + 0.04 V AINM/AINP Undervoltage Detect Level AVSS − 0.04 V INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 614.4 − 5% 614.4 614.4 + 5% kHz Duty Cycle 50:50 % External Clock Frequency 2.4576 MHz Internal divide by 4 Duty Cycle Range 45:55 to 55:45 % LOGIC INPUTS2 Input Voltage Low, VINL 0.3 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V 0.35 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V 0.7 V 2.3 V ≤ IOVDD ≤ 3.6 V High, VINH 0.7 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V 0.65 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V 1.7 V 2.3 V ≤ IOVDD < 2.7 V 2 V 2.7 V ≤ IOVDD ≤ 3.6 V Hysteresis 0.2 0.6 V 1.65 V ≤ IOVDD ≤ 3.6 V Input Currents −1 +1 μA VIN = IOVDD or GND Input Capacitance 10 pF All digital inputs Rev. 0 | Page 7 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
