Datasheet AD7949-EP (Analog Devices) - 6

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AD7949-EP Enhanced Product
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications −55°C to +125°C, unless otherwise noted.
Table 4. Parameter1 Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 3.2 µs Acquisition Time tACQ 1.8 µs Time Between Conversions tCYC 5 µs Data Write/Read During Conversion tDATA 1.2 µs CNV Pulse Width tCNVH 10 ns SCK Period tSCK tDSDO + 2 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 38 ns VIO Above 1.8 V 48 ns CNV Low to SDO D15 MSB Valid tEN VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns VIO Above 2.3 V 35 ns VIO Above 1.8 V 45 ns CNV High or Last SCK Fal ing Edge to SDO High Impedance tDIS 50 ns CNV Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns DIN Valid Hold Time from SCK Rising Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA IOL TO SDO 1.4V CL 50pF
002
500µA IOH
09822- Figure 2. Load Circuit for Digital Interface Timing
70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
003
2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
09822- Figure 3. Voltage Levels for Timing Rev. B | Page 6 of 12 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide