Datasheet AD7655-EP (Analog Devices) - 8

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AD7655-EP Enhanced Product PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ND A B G ND ND F F F F AG AG INA1 INAN INA2 RE RE INB2 INBN INB1 RE RE 48 47 46 45 44 43 42 41 40 39 38 37 ND 1 N 2 A B 2 N 1 G AGND 1 36 DVDD ND ND A A A F F B B B F F AVDD 2 35 CNVST AG AG IN IN IN RE RE IN IN IN RE RE A0 3 34 PD 48 47 46 45 44 43 42 41 40 39 38 37 BYTESWAP 4 33 RESET A/B 5 32 CS AGND 1 36 DVDD DGND 6 AD7655-EP AVDD 2 35 CNVST 31 RD A0 3 34 PD IMPULSE 7 TOP VIEW 30 EOC BYTESWAP 4 33 RESET (Not to Scale) SER/PAR 8 29 BUSY A/B 5 32 CS AD7655-EP D0 DGND RD 9 28 D15 6 31 IMPULSE 7 TOP VIEW 30 EOC D1 10 27 D14 SER/PAR 8 (Not to Scale) 29 BUSY D2/DIVSCLK[0] 11 26 D13 D0 9 28 D15 D3/DIVSCLK[1] 12 25 D12 D1 10 27 D14 D2/DIVSCLK[0] 11 26 D13 D3/DIVSCLK[1] 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 13 14 15 16 17 18 19 20 21 22 23 24 C K N D D K R N D ND UT T C K D D D K C R /INT N DD NC IN CL DI CL L D D ND UT L N O T Y Y D S S S /IN C C Y R X OG OV DV DG DO S RRO T S S OGN OV DV DG DO S S R E VS S X V D9/ VSYN S /IN INV RDC/ D10/ /E D9/ 10/ D4/ 5 D8/ RDE 4 /IN /IN 6 /RDC/ D8/ D RDE D D6/ D 5 D7/ D D 7 D D11/ D11/
5
NOTES
004
NOTES
00 0-
1. EXPOSED PAD. THE EPAD IS CONNECTED TO GROUND; HOWEVER, THIS CONNECTION
0-
1. EXPOSED PAD. THE EPAD IS CONNECTED TO GROUND; HOWEVER, THIS CONNECTION IS NOT REQUIRED TO MEET SPECIFIED PERFORMANCE.
0923
IS NOT REQUIRED TO MEET SPECIFIED PERFORMANCE.
0923 Figure 4. 48-Lead LFCSP (CP-48-1) Figure 5. 48-Lead LFCSP (CP-48-4)
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 47, 48 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 5 V. 3 A0 DI Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted. 4 BYTESWAP DI Parallel Mode Selection (8 Bit, 16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 A/B DI Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH, the data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by Channel B. When LOW, Channel B is output first followed by Channel A. 6, 20 DGND P Digital Power Ground. 7 IMPULSE DI Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after convert mode. These inputs, part of the serial port, are used to slow down the internal serial clock that clocks the data output. In the other serial modes, these inputs are not used. 13 D[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock called, respectively, master and slave mode. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. Rev. B | Page 8 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE