Data SheetADRF65200.50.5B)B)d0.4d0.4CH (CH (0.30.3ATATMMIS0.2IS0.2N MN M0.10.1AIAIGGL0L0–0.1–0.1CHANNE –0.2CHANNEO–0.2OTTLL–0.3–0.3–0.4–0.4CHANNECHANNE–0.5–0.500.250.500.751.001.251.50 005 00.250.500.751.001.251.50 008 VGN1 (V) 14830- VGN2 (V) 14830- Figure 9. Channel to Chanel Gain Mismatch vs. VGN1; VGN2 = 0 V, Figure 12. Channel to Channel Gain Mismatch vs. VGN2; VGN1 = 1.5 V, Bypass Mode at 500 MHz Bypass Mode at 500 MHz 6060VPS = 3.3V50VPS = 3.15V50VPS = 3.45V40BYPASST720MHzA = +85°C3040TA = +25°CT576MHzA = –40°C203010B)B)dd432MHz0N (20N (AIAIG–10G10288MHz–20–300–40–10144MHz36MHz 72MHz–50–60–2000.51.01.52.02.53.03.54.04.55.0 009 00.51.01.52.02.53.03.54.04.55.0 013 FREQUENCY (GHz) 14830- FREQUENCY (MHz) 14830- Figure 10. Gain vs. Frequency over VGN1/VGN2, 3 dB Gain Steps Figure 13. Frequency Response over Supply and Temperature for 36 MHz, 144 MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz Filter Corners and Bypass 5555.036MHz FILTER 72MHz FILTER54.5144MHz FILTER 288MHz FILTER 432MHz FILTER54.054576MHz FILTER 720MHz FILTER53.5FILTER BYPASS53.0B)B)dd53N (52.5N (AIAIGG 52.036MHz FILTER51.572MHz FILTER52144MHz FILTER51.0288MHz FILTER 432MHz FILTER 576MHz FILTER50.5720MHz FILTER FILTER BYPASS5150.01101001000 011 100300500700900110013001500 014 FREQUENCY (MHz) 14830- FREQUENCY (MHz) 14830- Figure 11. Gain vs. Frequency over all Bandwidth Settings; Figure 14. Gain vs. Frequency over all Bandwidth Settings; VGN1 = VGN2 = 1.5 V (Logarithmic) VGN1 = VGN2 = 1.5 V (Linear) Rev. 0 | Page 9 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VGAs RMS DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6520 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS SPI REGISTER AND TIMING REGISTER READ/WRITE TIMING Write Cycle Read Cycle APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING RMS DETECTOR CONNECTIONS VGA2 GAIN STEP RESPONSE LINEAR OPERATION OF THE ADRF6520 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE