Datasheet AD9675 (Analog Devices) - 4

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AD9675 Data Sheet SPECIFICATIONS AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), fIN = 5 MHz, low bandwidth mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = mid-high, PGA gain = 27 dB, analog gain control, VGAIN (V) = (GAIN+) − (GAIN−) = 1.6 V, AAF LPF cutoff = fSAMPLE/3 (Mode I/Mode II) = fSAMPLE/4.5 (Mode III/Mode IV), HPF cutoff = LPF cutoff/12.00, Mode I = fSAMPLE = 40 MSPS, Mode II = fSAMPLE = 65 MSPS, Mode III = fSAMPLE = 80 MSPS, Mode IV = 125 MSPS, RF decimator bypassed (Mode I/Mode II), RF decimator enabled (Mode III/Mode IV), digital high-pass filter bypassed, JESD204B link parameters: M = 8 and L = 2, unless otherwise noted. All gain setting options are listed, which can be configured via SPI registers, and all power supply currents and power dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV).
Table 1. Parameter1 T est Conditions/Comments Min Typ Max Unit
LNA CHARACTERISTICS Gain Single-ended input to differential output 15.6/17.9/21.6 dB Single-ended input to single-ended output 9.6/11.9/15.6 dB 0.1 dB Input Compression Point LNA gain = 15.6 dB 1000 mV p-p LNA gain = 17.9 dB 750 mV p-p LNA gain = 21.6 dB 450 mV p-p 1 dB Input Compression Point LNA gain = 15.6 dB 1200 mV p-p LNA gain = 17.9 dB 900 mV p-p LNA gain = 21.6 dB 600 mV p-p Input Common Mode (LI-x, LG-x) 2.2 V Output Common Mode (LO-x) Switch off High-Z Ω Switch on 1.5 V Output Common Mode (LOSW-x) Switch off High-Z Ω Switch on 1.5 V Input Resistance (LI-x) RFB = 300 Ω, LNA gain = 21.6 dB 50 Ω RFB = 1350 Ω, LNA gain = 21.6 dB 200 Ω 6 kΩ Input Capacitance (LI-x) 22 pF Input Referred Noise Voltage RS = 0 Ω LNA gain = 15.6 dB 0.83 nV/√Hz LNA gain = 17.9 dB 0.82 nV/√Hz LNA gain = 21.6 dB 0.78 nV/√Hz Input Signal-to-Noise Ratio Noise bandwidth = 15 MHz 94 dB Input Noise Current 2.6 pA/√Hz FULL CHANNEL CHARACTERISTICS Time gain control (TGC) AAF Low-Pass Cutoff −3 dB, programmable, low bandwidth mode 8 18 MHz −3 dB, programmable, high bandwidth mode 13.5 30 MHz In Range AAF Bandwidth ±10 % Tolerance Group Delay Variation f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V ±350 ps Input Referred Noise Voltage LNA gain = 15.6 dB 0.96 nV/√Hz LNA gain = 17.9 dB 0.90 nV/√Hz LNA gain = 21.6 dB 0.82 nV/√Hz Noise Figure Active Termination Matched LNA gain = 15.6 dB, RFB = 150 Ω 5.6 dB LNA gain = 17.9 dB, RFB = 200 Ω 4.8 dB LNA gain = 21.6 dB, RFB = 300 Ω 3.8 dB Unterminated LNA gain = 15.6 dB, RFB = ∞ 3.2 dB LNA gain = 17.9 dB, RFB = ∞ 2.9 dB LNA gain = 21.6 dB, RFB = ∞ 2.6 dB Rev. A | Page 4 of 60 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications AC Specifications Digital Specifications Switching Specifications CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Theory of Operation TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins Analog Test Tone Generation CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Digital RF Decimator Vector Profile RF Decimator DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter Digital Test Waveforms Waveform Generator Channel ID and Ramp Generator Digital Block Power Saving Scheme Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Recommended Start-Up Sequence Memory Map Register Table Memory Map Register Descriptions Transfer (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) Outline Dimensions Ordering Guide