Datasheet AD9257-EP (Analog Devices) - 10

AD9257-EP Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS F E F E E D D C C + – D – + D C S AS + – D – + N N D N N D N N N N D N N VI VI AV VI VI AV SY VCM VREF SE RBI VI VI AV VI VI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD 1 48 AVDD VIN+ G 2 47 VIN+ B VIN– G 3 46 VIN– B AVDD 4 45 AVDD VIN– H 5 44 VIN– A VIN+ H 6 43 VIN+ A AVDD 7 42 AVDD AD9257-EP AVDD 8 41 PDWN TOP VIEW CLK– 9 40 CSB (Not to Scale) CLK+ 10 39 SDIO/DFS AVDD 11 38 SCLK/DTP AVDD 12 37 AVDD NIC 13 36 NIC DRVDD 14 35 DRVDD D– H 15 34 D+ A D+ H 16 33 D– A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 – + + G F E O O– O D D C C B B D– G D+ D– F D+ D– E D+ D– D+ D– D+ D– D+ DCO DC FC FC NOTES 1. NIC = NOT INTERNALLY CONNECTED. THESE PINS CAN BE CONNECTED TO GROUND. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
-005
ANALOG GROUND FOR THE DEVICE. THIS EXPOSED PAD MUST BE CONNECTED TO
740
GROUND FOR PROPER OPERATION.
12 Figure 6. Pin Configuration, Top View
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
0 AGND, EP Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the analog ground for the device. This exposed pad must be connected to ground for proper operation. 1, 4, 7, 8, 11, 12, 37, AVDD 1.8 V Analog Supply. 42, 45, 48, 51, 59, 62 13, 36 NIC Not Internally Connected. These pins can be connected to ground. 14, 35 DRVDD 1.8 V Digital Output Driver Supply. 2, 3 VIN+ G, VIN− G ADC G Analog Input True, ADC G Analog Input Complement. 5, 6 VIN− H, VIN+ H ADC H Analog Input Complement, ADC H Analog Input True. 9, 10 CLK−, CLK+ Input Clock Complement, Input Clock True. 15, 16 D− H, D+ H ADC H Digital Output Complement, ADC H Digital Output True. 17, 18 D− G, D+ G ADC G Digital Output Complement, ADC G Digital Output True. 19, 20 D− F, D+ F ADC F Digital Output Complement, ADC F Digital Output True. 21, 22 D− E, D+ E ADC E Digital Output Complement, ADC E Digital Output True. 23, 24 DCO−, DCO+ Data Clock Digital Output Complement, Data Clock Digital Output True. 25, 26 FCO−, FCO+ Frame Clock Digital Output Complement, Frame Clock Digital Output True. 27, 28 D− D, D+ D ADC D Digital Output Complement, ADC D Digital Output True. 29, 30 D− C, D+ C ADC C Digital Output Complement, ADC C Digital Output True. 31, 32 D− B, D + B ADC B Digital Output Complement, ADC B Digital Output True. 33, 34 D− A, D+ A ADC A Digital Output Complement, ADC A Digital Output True. 38 SCLK/DTP Serial Clock (SCLK)/Digital Test Pattern (DTP). 39 SDIO/DFS Serial Data Input/Output (SDIO)/Data Format Select (DFS). 40 CSB Chip Select Bar. 41 PDWN Power-Down. 43, 44 VIN+ A, VIN− A ADC A Analog Input True, ADC A Analog Input Complement. 46, 47 VIN− B, VIN+ B ADC B Analog Input Complement, ADC B Analog Input True. 49, 50 VIN+ C, VIN− C ADC C Analog Input True, ADC C Analog Input Complement. Rev. A | Page 10 of 13 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE