Datasheet ADW12001 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Dual 14-Bit, 20/40/65 MSPS, 3 V Analog-to-Digital Converter |
| Pages / Page | 24 / 7 — ADW12001. SWITCHING SPECIFICATIONS. Table 4. Parameter. Temp. Min. Typ. … |
| File Format / Size | PDF / 678 Kb |
| Document Language | English |
ADW12001. SWITCHING SPECIFICATIONS. Table 4. Parameter. Temp. Min. Typ. Max Unit. Timing Diagram. N + 1. N + 2. N + 8. N – 1. N + 3. ANALOG. INPUT
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ADW12001 SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4. Parameter Temp Min Typ Max Unit
SWITCHING PERFORMANCE Maximum Conversion Rate Full 40 MSPS Minimum Conversion Rate Full 1 MSPS CLK Period Full 25.0 ns CLK Pulse Width High1 Full 8.8 ns CLK Pulse Width Low1 Full 8.8 ns DATA OUTPUT PARAMETER Output Delay2 (tPD) Full 2 3.5 6 ns Pipeline Delay (Latency) Full 7 Cycles Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (tJ) Full 0.5 ps rms Wake-Up Time3 Full 2.5 ms OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 This model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 16). 2 Output delay is measured from clock 50% transition to data 50% transition with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
Timing Diagram N N + 1 N + 2 N + 8 N – 1 N + 3 ANALOG INPUT N + 4 N + 7 N + 5 N + 6 CLOCK DATA OUT N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N
2
t MIN 2.0ns,
00
PD =
7-
MAX 6.0ns
73 07 Figure 2. Timing Diagram Rev. 0 | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
ADW12001 SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4. Parameter Temp Min Typ Max Unit
SWITCHING PERFORMANCE Maximum Conversion Rate Full 40 MSPS Minimum Conversion Rate Full 1 MSPS CLK Period Full 25.0 ns CLK Pulse Width High1 Full 8.8 ns CLK Pulse Width Low1 Full 8.8 ns DATA OUTPUT PARAMETER Output Delay2 (tPD) Full 2 3.5 6 ns Pipeline Delay (Latency) Full 7 Cycles Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (tJ) Full 0.5 ps rms Wake-Up Time3 Full 2.5 ms OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 This model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 16). 2 Output delay is measured from clock 50% transition to data 50% transition with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
Timing Diagram N N + 1 N + 2 N + 8 N – 1 N + 3 ANALOG INPUT N + 4 N + 7 N + 5 N + 6 CLOCK DATA OUT N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N
2
t MIN 2.0ns,
00
PD =
7-
MAX 6.0ns
73 07 Figure 2. Timing Diagram Rev. 0 | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
