Datasheet ADL5202 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Wide Dynamic Range, High Speed, Digitally Controlled VGA |
| Pages / Page | 29 / 4 — ADL5202. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. … |
| Revision | D |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
ADL5202. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit. Timing Diagrams. tSCLK. tPW. SCLK. tDH. tDS. ___ ___. CSA, CSB. tDS tDH
Model Line for this Datasheet
Text Version of Document
ADL5202 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
POWER-UP INTERFACE PWUPA, PWUPB pins Power-Up Threshold Minimum voltage to enable the device 1.4 V Maximum voltage to enable the device 3.3 V PWUPx Input Bias Current 1 μA GAIN CONTROL INTERFACE VIH Minimum/Maximum voltage for a logic high 1.41 3.3 V VIL Maximum voltage for a logic low 0.8 Maximum Input Bias Current 1 μA SPI TIMING LATCHA and LATCHB, SCLK, SDIO, data pins fSCLK 1/tSCLK 20 MHz tDH Data hold time 5 ns tDS Data setup time 5 ns tPW SCLK high pulse width 5 ns POWER INTERFACE Supply Voltage 4.5 5.5 V Quiescent Current, Both Channels High performance mode 210 mA TA = 85°C 250 mA Low power mode 160 mA TA = 85°C 180 mA Power-Down Current, Both Channels PWUPx low 14 mA 1 The minimum value for a logic high on the PM pin is 2.8 V.
Timing Diagrams tSCLK tPW SCLK tDH tDS ___ ___ CSA, CSB tDS tDH
02
SDIO DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0
-0 9387 0 Figure 2. SPI Interface Read/Write Mode Timing Diagram
tDS tDS UPDN_DAT tPW UPDN_CLK UP DN RESET
103
t
7-
DS tDH
938 0 Figure 3. Up/Down Mode Timing Diagram
LATCHA, LATCHB A5 TO A0 B5 TO B0
104 87-
tDH
093 Figure 4. Parallel Mode Timing Diagram Rev. D | Page 4 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack GAIN UP/DOWN INTERFACE TRUTH TABLE LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE Input System Output Amplifier Gain Control APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE EVALUATION BOARD SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE
POWER-UP INTERFACE PWUPA, PWUPB pins Power-Up Threshold Minimum voltage to enable the device 1.4 V Maximum voltage to enable the device 3.3 V PWUPx Input Bias Current 1 μA GAIN CONTROL INTERFACE VIH Minimum/Maximum voltage for a logic high 1.41 3.3 V VIL Maximum voltage for a logic low 0.8 Maximum Input Bias Current 1 μA SPI TIMING LATCHA and LATCHB, SCLK, SDIO, data pins fSCLK 1/tSCLK 20 MHz tDH Data hold time 5 ns tDS Data setup time 5 ns tPW SCLK high pulse width 5 ns POWER INTERFACE Supply Voltage 4.5 5.5 V Quiescent Current, Both Channels High performance mode 210 mA TA = 85°C 250 mA Low power mode 160 mA TA = 85°C 180 mA Power-Down Current, Both Channels PWUPx low 14 mA 1 The minimum value for a logic high on the PM pin is 2.8 V.
Timing Diagrams tSCLK tPW SCLK tDH tDS ___ ___ CSA, CSB tDS tDH
02
SDIO DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0
-0 9387 0 Figure 2. SPI Interface Read/Write Mode Timing Diagram
tDS tDS UPDN_DAT tPW UPDN_CLK UP DN RESET
103
t
7-
DS tDH
938 0 Figure 3. Up/Down Mode Timing Diagram
LATCHA, LATCHB A5 TO A0 B5 TO B0
104 87-
tDH
093 Figure 4. Parallel Mode Timing Diagram Rev. D | Page 4 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack GAIN UP/DOWN INTERFACE TRUTH TABLE LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE Input System Output Amplifier Gain Control APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE EVALUATION BOARD SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE
