Datasheet ADL5201 (Analog Devices) - 3

Data Sheet ADL5201 SPECIFICATIONS
VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 100 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth VOUT < 2 V p-p (5.2 dBm) 700 MHz Slew Rate 5.5 V/ns Input Return Loss (S11) 100 MHz −18.73 dB Output Return Loss (S22) 100 MHz −18.8 dB INPUT STAGE VIN+ and VIN− pins Maximum Input Swing (Differential) Gain code = 111111 10.8 V p-p Differential Input Resistance 150 Ω Common-Mode Input Voltage 1.5 V CMRR Gain code = 000000 51.44 dB GAIN Maximum Voltage Gain Gain code = 000000 20 dB Minimum Voltage Gain Gain code = 111111 −11.5 dB Gain Step Size 0.5 dB Gain Flatness 30 MHz < fC < 200 MHz 0.285 dB Gain Temperature Sensitivity Gain code = 000000 0.0089 dB/°C Gain Step Response For VIN = 0.2 V, gain code = 111111 to 000000 15 ns Gain Conformance Error Over 10 dB gain range ±0.03 dB Phase Conformance Error Over 10 dB gain range 1.0 Degrees OUTPUT STAGE VOUT+ and VOUT− pins Output Voltage Swing At P1dB, gain code = 000000 10 V p-p Differential Output Resistance Differential 150 Ω NOISE/HARMONIC PERFORMANCE 46 MHz Gain code = 000000, high performance mode Second Harmonic VOUT = 2 V p-p −86 dBc Third Harmonic VOUT = 2 V p-p −104 dBc Output IP3 (OIP3) VOUT = 2 V p-p composite 50 dBm 70 MHz Gain code = 000000, high performance mode Second Harmonic VOUT = 2 V p-p −91 dBc Third Harmonic VOUT = 2 V p-p −103 dBc Output IP3 (OIP3) VOUT = 2 V p-p composite 51 dBm 140 MHz Gain code = 000000, high performance mode Noise Figure 7.5 dB Second Harmonic VOUT = 2 V p-p −89 dBc Third Harmonic VOUT = 2 V p-p −97 dBc Output IP3 (OIP3) VOUT = 2 V p-p composite 51 dBm Output 1 dB Compression Point (OIP1dB) 19.8 dBm 300 MHz Gain code = 000000, high performance mode Second Harmonic VOUT = 2 V p-p −85 dBc Third Harmonic VOUT = 2 V p-p −90 dBc Output IP3 (OIP3) VOUT = 2 V p-p composite 50 dBm Rev. C | Page 3 of 26 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack UP/DOWN INTERFACE Truth Table LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE INPUT SYSTEM OUTPUT AMPLIFIER GAIN CONTROL APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE