Datasheet AD8260 (Analog Devices) - 5

Data Sheet AD8260 Parameter Test Conditions/Comments Min Typ Max Unit
Overload Recovery Maximum gain (gain code = 1011), gain = 24 dB, 50 ns VIN = 50 mV p-p to 500 mV p-p Group Delay Variation 1 MHz < f < 50 MHz, full gain range 2 ns ACCURACY Absolute Gain Error All gain codes, limits are 3σ −0.5 ±0.15 +0.5 dB Gain Law Conformance (DNL) Differential gain error, code to code −0.3 ±0.15 +0.3 dB GAIN CONTROL Gain Step per Code 3.0 dB Gain Range Default = −6 dB to +24 dB 30 dB Response Time 30 dB gain change (gain code stepped from 0001 to 1011) 50 ns LOGIC INTERFACES High Level Input Voltage 1.4 VS V Low Level Input Voltage 0 0.8 V Logic Input Bias Current Logic high, VLOGIC = 3.3 V 0.2 µA Logic low 18 nA POWER SUPPLY Supply Voltage Single supply 3.3 10 V Dual supply ±3.3 ±5 V Quiescent Current Full chip enabled (TXEN = 1, ENBL = 1, gain code = 0001) 28.3 mA TXEN = 0, ENBL = 1, gain code = 0001, driver off, DGA on 19.1 mA TXEN = 1, ENBL = 1, gain code = 0000, driver on, DGA off 10.8 mA Chip disabled (TXEN = 0, ENBL = 0, gain code = 0000) 35 µA VS = ±5 V, no signal 34.2 mA PSRR Maximum gain (gain code = 1011), gain = 24 dB, 1 MHz −30 dB Driver amplifier, 1 MHz −48 dB Power Dissipation No signal 93 mW No signal, VPOS − VNEG = 10 V 342 mW ENABLE TIMES Chip Enable Time Bias only, TXEN = 0, gain code = 0000, ENBL = 0 to 1 0.4 µs All at once, TXEN = 0 to 1, gain code = 0000 to 0001, 0.3 µs ENBL = 0 to 1 Preamplifier and DGA Enable Time ENBL = 1, TXEN = 0, gain code = 0000 to 0001 0.3 µs Driver Enable Time ENBL = 1, gain code = 0001, TXEN stepped from 0 to 1 0.2 µs DISABLE TIMES Chip Disable Time TXEN = 1 to 0, gain code = 0001 to 0000, 20 µs ENBL = 1 to 0, ISUPPLY = 100 µA All at once, TXEN = 1 to 0, gain code = 0001 to 0000, 50 µs ENBL = 1 to 0, ISUPPLY = 35 µA Preamplifier and DGA Disable Time ENBL = 1, TXEN = 0, gain code = 0001 to 0000 0.4 µs Driver Disable Time ENBL = 1, gain code = 0000, TXEN = 1 to 0 2.2 µs Rev. B | Page 5 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION OVERVIEW HIGH CURRENT DRIVER AMPLIFIER PRECAUTIONS TO BE OBSERVED DURING HALF-DUPLEX OPERATION VMID BUFFER PREAMPLIFIER PREAMPLIFIER NOISE DGA GAIN CONTROL OUTPUT STAGE ATTENUATOR SINGLE-SUPPLY OPERATION AND AC COUPLING POWER-UP/POWER-DOWN SEQUENCE LOGIC INTERFACES APPLICATIONS INFORMATION EVALUATION BOARD CONNECTING THE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE