Datasheet AD8260 (Analog Devices) - 7

Data Sheet AD8260 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS M C P N B PIN 1 P P F INDICATOR VO INRN INRP IN IN TX VNEG VNEG 32 31 30 29 28 27 26 25 VMDO 1 24 TXOP TXEN 2 23 TXOP VMDI 3 22 VPOS VNCM AD8260 4 21 VPOS VPSB 5 TOP VIEW 20 VPSR (Not to Scale) ENBL 6 19 VMDO VGAP 7 18 PRAI VGAN 8 17 FDBK 9 10 11 12 13 14 15 16 R 3 2 1 0 R G S S S S G RAO VN VPSR GN GN GN GN P VN NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
02 0
THE GROUND PLANE PATTERN SHOULD INCLUDE A
2-
PATTERN OF VIAS TO INNER LAYERS.
719 0 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 191 VMDO VMID Buffer Output. Requires robust ac decoupling with a capacitance of 0.1 μF capacitor or greater. 2 TXEN Driver Enable. Logic threshold = 1.1 V with ±0.2 V hysteresis. 3 VMDI VMID Input Voltage. Normally decoupled with a 0.1 μF capacitor. When pulled to VNCM, the VMID buffer shuts down. This can be useful when using the part with dual supplies or when an external midpoint generator is used. 4 VNCM Negative Supply for Bias Cell, VMID Cell, and Logic Inputs. (Ground this pin in applications.) 5 VPSB Positive Supply for Bias Cell and VMID Cell. 6 ENBL Enable. Logic threshold = 1.1 V. When low, the AD8260 is disabled and the supply current is 35 μA when TXEN and all GNSx pins are also low. 7 VGAP Positive VGA Output (Needs to Be Ac-Coupled for Single Supply). 8 VGAN Negative VGA Output (Needs to Be Ac-Coupled for Single Supply). 9, 161 VNGR Negative Supply for Preamplifier and DGA (Set to −VPOS for Dual Supply; GND for Single Supply). 10, 201 VPSR Positive Supply for Preamplifier, DGA, and GNSx Logic Decoder. 11 GNS3 MSB for Gain Control. Logic threshold = 1.1 V. 12 GNS2 Gain Control Bit. Logic threshold = 1.1 V. 13 GNS1 Gain Control Bit. Logic threshold = 1.1 V. 14 GNS0 LSB for Gain Control. Logic threshold = 1.1 V. 15 PRAO Preamplifier Output. 17 FDBK Negative Input of Preamplifier. 18 PRAI Positive Input of Preamplifier. 21, 221 VPOS Positive Supply for Driver Amplifier. 23, 241 TXOP Driver Output. 25, 261 VNEG Negative Supply for Driver Amplifier (Set to −VPOS for Dual Supply; GND for Single Supply). 27 TXFB Feedback for Driver Amplifier. 28 INPN Negative Driver Amplifier Input. 29 INRN Negative Gain Resistor Input for Driver Amplifier. 30 INRP Positive Gain Resistor Input for Driver Amplifier. 31 INPP Positive Driver Amplifier Input. 32 VOCM Output Common Mode Pin. Normally connected to Pin VMDO. EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability it is recommended that the pad be soldered to the ground plane. The ground plane pattern should include a pattern of vias to inner layers. 1 Pins with the same name are connected internally. Rev. B | Page 7 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION OVERVIEW HIGH CURRENT DRIVER AMPLIFIER PRECAUTIONS TO BE OBSERVED DURING HALF-DUPLEX OPERATION VMID BUFFER PREAMPLIFIER PREAMPLIFIER NOISE DGA GAIN CONTROL OUTPUT STAGE ATTENUATOR SINGLE-SUPPLY OPERATION AND AC COUPLING POWER-UP/POWER-DOWN SEQUENCE LOGIC INTERFACES APPLICATIONS INFORMATION EVALUATION BOARD CONNECTING THE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE