Datasheet ADN2891 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 3.3 V, 3.2 Gbps Limiting Amplifier |
| Pages / Page | 16 / 6 — ADN2891. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. HO T. … |
| Revision | B |
| File Format / Size | PDF / 603 Kb |
| Document Language | English |
ADN2891. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. HO T. I_O S. D_C. D_V. AVCC 1. 12 DRVCC. PIN 2. 11 OUTP. NIN 3. TOP VIEW
Model Line for this Datasheet
Text Version of Document
ADN2891 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DE HO T UT CH A CC L I_O S UE D_C D_V Q P P RS S 16 15 14 13 AVCC 1 12 DRVCC PIN 2 11 OUTP ADN2891 NIN 3 TOP VIEW 10 OUTN (Not to Scale) AVEE 4 9 DRVEE 5 6 7 8 1 2 LOS CAZ CAZ HRADJ T NOTES 1. THE LFCSP HAS AN EXPOSED PAD ON THE BOTTOM. TO IMPROVE HEAT DISSIPATION, THE EXPOSED PAD MUST BE SOLDERED TO THE GND PLANE WITH FILLED VIAS.
Figure 2. Pin Configuration Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane with filled vias.
Table 4. Pin Function Descriptions Pin No. Mnemonic I/O Type1 Descriptions
1 AVCC P Analog Power Supply. 2 PIN AI Differential Data Input, Positive Port, 50 Ω On-Chip Termination. 3 NIN AI Differential Data Input, Negative Port, 50 Ω On-Chip Termination. 4 AVEE P Analog Ground. 5 THRADJ AO LOS Threshold Adjust Resistor. 6 CAZ1 AI If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for input offset correction. 7 CAZ2 AI If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for input offset correction. 8 LOS DO LOS Detector Output, Open Collector. 9 DRVEE P Output Buffer Ground. 10 OUTN DO Differential Data Output, CML, Negative Port, 50 Ω On-Chip Termination. 11 OUTP DO Differential Data Output, CML, Positive Port, 50 Ω On-Chip Termination. 12 DRVCC P Output Buffer Power Supply. 13 SQUELCH DI Disable Outputs, 100 kΩ On-Chip Pull-Down Resistor. 14 RSSI_OUT AO Average Current Output. 15 PD_VCC P Power Input for RSSI Measurement. 16 PD_CATHODE AO Photodiode Bias Voltage. Exposed Pad P Connect to Ground. Pad 1 P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output. Rev. B | Page 6 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMITING AMPLIFIER Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS PCB DESIGN GUIDELINES Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
Figure 2. Pin Configuration Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane with filled vias.
Table 4. Pin Function Descriptions Pin No. Mnemonic I/O Type1 Descriptions
1 AVCC P Analog Power Supply. 2 PIN AI Differential Data Input, Positive Port, 50 Ω On-Chip Termination. 3 NIN AI Differential Data Input, Negative Port, 50 Ω On-Chip Termination. 4 AVEE P Analog Ground. 5 THRADJ AO LOS Threshold Adjust Resistor. 6 CAZ1 AI If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for input offset correction. 7 CAZ2 AI If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for input offset correction. 8 LOS DO LOS Detector Output, Open Collector. 9 DRVEE P Output Buffer Ground. 10 OUTN DO Differential Data Output, CML, Negative Port, 50 Ω On-Chip Termination. 11 OUTP DO Differential Data Output, CML, Positive Port, 50 Ω On-Chip Termination. 12 DRVCC P Output Buffer Power Supply. 13 SQUELCH DI Disable Outputs, 100 kΩ On-Chip Pull-Down Resistor. 14 RSSI_OUT AO Average Current Output. 15 PD_VCC P Power Input for RSSI Measurement. 16 PD_CATHODE AO Photodiode Bias Voltage. Exposed Pad P Connect to Ground. Pad 1 P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output. Rev. B | Page 6 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMITING AMPLIFIER Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS PCB DESIGN GUIDELINES Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
