Datasheet ADN2891 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 3.3 V, 3.2 Gbps Limiting Amplifier |
| Pages / Page | 16 / 8 — ADN2891. Data Sheet. 5.0. 4.5. –40. 4.0. +95. 3.5. +25. 3.0. 2.5. 2.0. … |
| Revision | B |
| File Format / Size | PDF / 603 Kb |
| Document Language | English |
ADN2891. Data Sheet. 5.0. 4.5. –40. 4.0. +95. 3.5. +25. 3.0. 2.5. 2.0. DEASSERTION. RANDOM JITTER (ps). 1.5. LOS TRIP AND RELEASE (mV). 1.0. 0.5. ASSERTION
Model Line for this Datasheet
Text Version of Document
ADN2891 Data Sheet 70 5.0 4.5 60 –40
°
C 4.0 50 +95
°
C 3.5 +25
°
C 3.0 40 2.5 +95
°
C 30 2.0 +25
°
C DEASSERTION 20 RANDOM JITTER (ps) 1.5 –40
°
C LOS TRIP AND RELEASE (mV) 1.0 10 0.5 ASSERTION 0
05244-011
0
05244-010
1k 10k 100k 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 RTH (
Ω
) DATA RATE (Gbps)
Figure 8. LOS Trip and Release vs. RTH at OC48 Figure 11. Random Jitter vs. Data Rate
8 14 OC48 12 6 10 OC3 8 4 6 4 2 DETERMINISTIC JITTER (ps) LOS ELECTRICAL HYSTERESIS (dB) 2 0
05244-012
0
05244-013
1k 10k 100k 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 R DATA RATE (Gbps) TH (
Ω
)
Figure 9. LOS Electrical Hysteresis vs. RTH at 25°C Figure 12. Deterministic Jitter vs. Data Rate
18 70 16 60 14 50 12 40 10 30 SAMPLE 8 20 6 10 POWER SUPPLY-NOISE REJECTION (dB) 4 0
05244-005
2 100k 1M 10M SUPPLY-NOISE FREQUENCY (Hz) 0
05244-022
6.0 6.3 6.6 6.9 7.2 7.5 7.8 8.1 8.4 8.7 9.0 ELECTRICAL HYSTERESIS (dB)
Figure 10. Sample Lot Distribution—Worst-Case Condition: Conditions = 155 Mbps, 100 kΩ @ 95°C, 3.6 V Figure 13. PSRR vs. Supply-Noise Frequency Rev. B | Page 8 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMITING AMPLIFIER Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS PCB DESIGN GUIDELINES Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
°
C 4.0 50 +95
°
C 3.5 +25
°
C 3.0 40 2.5 +95
°
C 30 2.0 +25
°
C DEASSERTION 20 RANDOM JITTER (ps) 1.5 –40
°
C LOS TRIP AND RELEASE (mV) 1.0 10 0.5 ASSERTION 0
05244-011
0
05244-010
1k 10k 100k 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 RTH (
Ω
) DATA RATE (Gbps)
Figure 8. LOS Trip and Release vs. RTH at OC48 Figure 11. Random Jitter vs. Data Rate
8 14 OC48 12 6 10 OC3 8 4 6 4 2 DETERMINISTIC JITTER (ps) LOS ELECTRICAL HYSTERESIS (dB) 2 0
05244-012
0
05244-013
1k 10k 100k 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 R DATA RATE (Gbps) TH (
Ω
)
Figure 9. LOS Electrical Hysteresis vs. RTH at 25°C Figure 12. Deterministic Jitter vs. Data Rate
18 70 16 60 14 50 12 40 10 30 SAMPLE 8 20 6 10 POWER SUPPLY-NOISE REJECTION (dB) 4 0
05244-005
2 100k 1M 10M SUPPLY-NOISE FREQUENCY (Hz) 0
05244-022
6.0 6.3 6.6 6.9 7.2 7.5 7.8 8.1 8.4 8.7 9.0 ELECTRICAL HYSTERESIS (dB)
Figure 10. Sample Lot Distribution—Worst-Case Condition: Conditions = 155 Mbps, 100 kΩ @ 95°C, 3.6 V Figure 13. PSRR vs. Supply-Noise Frequency Rev. B | Page 8 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMITING AMPLIFIER Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS PCB DESIGN GUIDELINES Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
