Datasheet ADN2890 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 3.3 V 2.7 Gb/s Limiting Amplifier |
| Pages / Page | 12 / 9 — Data Sheet. ADN2890. APPLICATIONS INFORMATION PCB DESIGN GUIDELINES. … |
| Revision | B |
| File Format / Size | PDF / 350 Kb |
| Document Language | English |
Data Sheet. ADN2890. APPLICATIONS INFORMATION PCB DESIGN GUIDELINES. Power Supply Connections and Ground Planes. VCC
Model Line for this Datasheet
Text Version of Document
link to page 9
Data Sheet ADN2890 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal greatly enhances the reliability of the connectivity of the performance. exposed pad to the GND plane during reflow.
Power Supply Connections and Ground Planes
Use of a 10 μF electrolytic capacitor between VCC and VEE is Use of one low impedance ground plane is recommended. The recommended at the location where the 3.3 V supply enters the VEE pins should be soldered directly to the ground plane to PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they reduce series inductance. If the ground plane is an internal should be placed between the IC power supply VCC and VEE, plane and connections to the ground plane are made through as close as possible to the ADN2890 VCC pins. vias, multiple vias can be used in parallel to reduce the series If connections to the supply and ground are made through vias, inductance, especially on Pin 9, which is the ground return for the use of multiple vias in parallel helps to reduce series the output buffers. The exposed pad should be connected to the inductance, especially on Pin 12, which supplies power to the GND plane using filled vias so that solder does not leak through high speed OUTP/OUTN output buffers. Refer to the schematic the vias during reflow. Using filled vias under the package in Figure 8 for recommended connections.
VCC C9 VCC DE RSSI MEASUREMENT TO ADC HO T H R1 C10 0.1
F T C U C 200 A O C VC _ EL _ U VCC D_ SSI P PD R SQ VCC C5 C6 16 15 14 13 C7 C8 AVCC DRVCC 1 12 C1 PIN CONNECT OUTP C3 2 11 EXPOSED TO HOST PAD TO C2 NIN OUTN C4 BOARD ADN2880 3 GND 10 AVEE DRVEE 4 9 5 6 7 8 1 2 S DJ Z Z LO CA CA C1–C4, C11: 0.01
F X5R/X7R DIELECTRIC, 0201 CASE HRA C5, C7, C9, C10, C12: 0.1
F X5R/X7R DIELECTRIC, 0402 CASE T C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE C11 R3 C12 R2 4.7k TO 10k ON HOST BOARD
-007 0 9-
VCC
450 0 Figure 8. Typical ADN2890 Applications Circuit Rev. B | Page 9 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMAMP Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes PCB Layout Soldering Guidelines for Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE NOTES
Data Sheet ADN2890 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal greatly enhances the reliability of the connectivity of the performance. exposed pad to the GND plane during reflow.
Power Supply Connections and Ground Planes
Use of a 10 μF electrolytic capacitor between VCC and VEE is Use of one low impedance ground plane is recommended. The recommended at the location where the 3.3 V supply enters the VEE pins should be soldered directly to the ground plane to PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they reduce series inductance. If the ground plane is an internal should be placed between the IC power supply VCC and VEE, plane and connections to the ground plane are made through as close as possible to the ADN2890 VCC pins. vias, multiple vias can be used in parallel to reduce the series If connections to the supply and ground are made through vias, inductance, especially on Pin 9, which is the ground return for the use of multiple vias in parallel helps to reduce series the output buffers. The exposed pad should be connected to the inductance, especially on Pin 12, which supplies power to the GND plane using filled vias so that solder does not leak through high speed OUTP/OUTN output buffers. Refer to the schematic the vias during reflow. Using filled vias under the package in Figure 8 for recommended connections.
VCC C9 VCC DE RSSI MEASUREMENT TO ADC HO T H R1 C10 0.1
F T C U C 200 A O C VC _ EL _ U VCC D_ SSI P PD R SQ VCC C5 C6 16 15 14 13 C7 C8 AVCC DRVCC 1 12 C1 PIN CONNECT OUTP C3 2 11 EXPOSED TO HOST PAD TO C2 NIN OUTN C4 BOARD ADN2880 3 GND 10 AVEE DRVEE 4 9 5 6 7 8 1 2 S DJ Z Z LO CA CA C1–C4, C11: 0.01
F X5R/X7R DIELECTRIC, 0201 CASE HRA C5, C7, C9, C10, C12: 0.1
F X5R/X7R DIELECTRIC, 0402 CASE T C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE C11 R3 C12 R2 4.7k TO 10k ON HOST BOARD
-007 0 9-
VCC
450 0 Figure 8. Typical ADN2890 Applications Circuit Rev. B | Page 9 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMAMP Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes PCB Layout Soldering Guidelines for Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE NOTES
