Datasheet ADN2890 (Analog Devices) - 10

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ADN2890 Data Sheet PCB Layout
50 Ω resistors connected between the output pin and VCC. The high speed inputs, PIN and NIN, are internally terminated with Figure 9 shows a recommended PC board layout. Use of 50 Ω 50 Ω to an internal reference voltage. transmission lines is required for al high frequency input and output signals to minimize reflections: PIN, NIN, OUTP and As with any high speed mixed-signal design, take care to keep OUTN. It is also necessary for the PIN/NIN input traces to be all high speed digital traces away from sensitive analog nodes. matched in length, and OUTP/OUTN output traces to be matched
Soldering Guidelines for Chip Scale Package
in length to avoid skew between the differential traces. C1, C2, The lands on the 16 LFCSP are rectangular. The printed circuit C3, and C4 are ac-coupling capacitors in series with the high board pad for these should be 0.1 mm longer than the package speed I/O. It is recommended that components be used such land length and 0.05 mm wider than the package land width. that the pad for the capacitor is the same width as the transmission The land should be centered on the pad. This ensures that the line in order to minimize the mismatch in the 50 Ω transmission solder joint size is maximized. The bottom of the chip scale line at the capacitor’s pads. It is recommended that the trans- package has a central exposed pad. The pad on the printed mission lines not change layers through vias, if possible. For circuit board should be at least as large as this exposed pad. The supply decoupling, the 1 nF decoupling capacitor should be user must connect the exposed pad to VEE using fil ed vias so placed on the same layer as the ADN2890 as close as possible to that solder does not leak through the vias during reflow. This the VCC pin. The 0.1 µF capacitor can be placed on the bottom ensures a solid connection from the exposed pad to VEE. of the PCB directly underneath the 1 nF decoupling capacitor. Al high speed CML outputs are back-terminated on chip with
R1, C9, C10 ON BOTTOM TO ROSA DOUBLE-VIAS TO REDUCE INDUCTANCE TO SUPPLY AND GND PLACE C5 ON PLACE C7 ON BOTTOM OF BOARD BOTTOM OF BOARD UNDERNEATH C6 1 EXPOSED PAD UNDERNEATH C8 C1 C6 C8 C3 PIN OUTP VIAS TO
∼
4mm GND NIN OUTN C2 C4 DOUBLE-VIA TO GND TO REDUCE INDUCTANCE VIA TO C12, R2 ON BOTTOM C11 VIA TO BOTTOM
04509-0-008 Figure 9. Recommended ADN2890 PCB Layout Rev. B | Page 10 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMAMP Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes PCB Layout Soldering Guidelines for Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE NOTES