Datasheet ADIS16365 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Six Degrees of Freedom Inertial Sensor |
| Pages / Page | 21 / 6 — ADIS16365. Data Sheet. TIMING SPECIFICATIONS. Table 2. Normal Mode. Low … |
| Revision | F |
| File Format / Size | PDF / 752 Kb |
| Document Language | English |
ADIS16365. Data Sheet. TIMING SPECIFICATIONS. Table 2. Normal Mode. Low Power Mode. (SMPL_PRD ≤ 0x09). (SMPL_PRD ≥ 0x0A). Burst Read
Model Line for this Datasheet
Text Version of Document
ADIS16365 Data Sheet TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2. Normal Mode Low Power Mode (SMPL_PRD ≤ 0x09) (SMPL_PRD ≥ 0x0A) Burst Read Parameter Description Min1 Typ Max Min1 Typ Max Min1 Typ Max Unit
fSCLK Serial clock 0.01 2.0 0.01 0.3 0.01 1.0 MHz tSTALL Stall period between data 9 75 1/fSCLK μs tREADRATE Read rate 40 100 μs t Chip select to SCLK edge 48.8 48.8 48.8 ns CS tDAV DOUT valid after SCLK edge 100 100 100 ns tDSU DIN setup time before SCLK rising edge 24.4 24.4 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 48.8 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 5 5 5 ns t1 Input sync positive pulse width 5 5 μs tx Input sync low time 100 100 μs t2 Input sync to data ready output 600 600 μs t3 Input sync period 833 833 μs 1 Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB tDSU tDHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
02 0 0- 757 0 Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS
03
SCLK
0 0- 57 07 Figure 3. Stall Time and Data Rate
t3 t2 t1 tX SYNC CLOCK (DIO4)
004
DATA
0-
READY
57 07 Figure 4. Input Clock Timing Diagram Rev. F | Page 6 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC OPERATION READING SENSOR DATA DEVICE CONFIGURATION MEMORY MAP BURST READ DATA COLLECTION OUTPUT DATA REGISTERS CALIBRATION Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) OPERATIONAL CONTROL Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range INPUT/OUTPUT FUNCTIONS General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC DIAGNOSTICS Self-Test Memory Test Status Alarm Registers PRODUCT IDENTIFICATION APPLICATIONS INFORMATION INSTALLATION AND HANDLING GYROSCOPE BIAS OPTIMIZATION INPUT ADC CHANNEL PC-BASED EVALUATION TOOLS X-RAY SENSITIVITY OUTLINE DIMENSIONS ORDERING GUIDE
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2. Normal Mode Low Power Mode (SMPL_PRD ≤ 0x09) (SMPL_PRD ≥ 0x0A) Burst Read Parameter Description Min1 Typ Max Min1 Typ Max Min1 Typ Max Unit
fSCLK Serial clock 0.01 2.0 0.01 0.3 0.01 1.0 MHz tSTALL Stall period between data 9 75 1/fSCLK μs tREADRATE Read rate 40 100 μs t Chip select to SCLK edge 48.8 48.8 48.8 ns CS tDAV DOUT valid after SCLK edge 100 100 100 ns tDSU DIN setup time before SCLK rising edge 24.4 24.4 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 48.8 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 5 5 5 ns t1 Input sync positive pulse width 5 5 μs tx Input sync low time 100 100 μs t2 Input sync to data ready output 600 600 μs t3 Input sync period 833 833 μs 1 Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB tDSU tDHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
02 0 0- 757 0 Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS
03
SCLK
0 0- 57 07 Figure 3. Stall Time and Data Rate
t3 t2 t1 tX SYNC CLOCK (DIO4)
004
DATA
0-
READY
57 07 Figure 4. Input Clock Timing Diagram Rev. F | Page 6 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC OPERATION READING SENSOR DATA DEVICE CONFIGURATION MEMORY MAP BURST READ DATA COLLECTION OUTPUT DATA REGISTERS CALIBRATION Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) OPERATIONAL CONTROL Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range INPUT/OUTPUT FUNCTIONS General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC DIAGNOSTICS Self-Test Memory Test Status Alarm Registers PRODUCT IDENTIFICATION APPLICATIONS INFORMATION INSTALLATION AND HANDLING GYROSCOPE BIAS OPTIMIZATION INPUT ADC CHANNEL PC-BASED EVALUATION TOOLS X-RAY SENSITIVITY OUTLINE DIMENSIONS ORDERING GUIDE
