Datasheet ADIS16365 (Analog Devices) - 10

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ADIS16365 Data Sheet THEORY OF OPERATION BASIC OPERATION
The user registers provide addressing for all input/output The ADIS16365 is an autonomous sensor system that starts up operations on the SPI interface. Each 16-bit register has two after they have a valid power supply voltage and begin producing 7-bit addresses: one for its upper byte and one for its lower inertial measurement data at the factory default sample rate byte. Table 8 lists the lower byte address for each register, and setting of 819.2 SPS. After each sample cycle, the sensor data is Figure 10 shows the generic bit assignments. loaded into the output registers, and DIO1 pulses high, which
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
provides a new data ready control signal for driving system- -010 level interrupt service routines. In a typical system, a master
UPPER BYTE LOWER BYTE
07570 processor accesses the output data registers through the SPI Figure 10. Generic Register Bit Assignments interface, using the connection diagram shown in Figure 9.
READING SENSOR DATA
Table 6 provides a generic functional description for each pin on Although the ADIS16365 produces data independently, they the master processor. Table 7 describes the typical master processor operate as SPI slave devices that communicate with system settings that are normally found in a configuration register and (master) processors using the 16-bit segments displayed in used for communicating with the ADIS16365. Figure 11. Individual register reads require two of these 16-bit
I/O LINES ARE COMPATIBLE WITH 5V
sequences. The first 16-bit sequence contains the read command
VDD 3.3V OR 5V LOGIC LEVELS
bit (R/W = 0) and the target register address (A6 to A0); the last
10 11 12
eight bits are “don’t care” bits when requesting a read. The second
SYSTEM PROCESSOR SS 6 CS
16-bit sequence transmits the register contents (D15 to D0) on
SPI MASTER ADIS16365 SCLK 3 SCLK SPI SLAVE
the DOUT line. For example, if DIN = 0x0A00, the contents of
MOSI 5 DIN
the XACCL_OUT register are shifted out on the DOUT line
MISO 4 DOUT
during the next 16-bit sequence.
IRQ 7 DIO1
The SPI operates in full-duplex mode, which means that the
13 14 15
master processor can read the output data from DOUT while 9 00 using the same SCLK pulses to transmit the next target address 0- 57 07 on DIN. Figure 9. Electrical Connection Diagram
DEVICE CONFIGURATION Table 6. Generic Master Processor Pin Names and Functions
The user register memory map (see Table 8) identifies configu-
Pin Name Function
ration registers with either a W or R/W. Configuration commands SS Slave select also use the bit sequence shown in Figure 11. If the MSB = 1, the SCLK Serial clock last eight bits (DC7 to DC0) in the DIN sequence are loaded into MOSI Master output, slave input the memory address associated with the address bits (A6 to A0). MISO Master input, slave output For example, if DIN = 0xA11F, 0x1F is loaded into Address 0x21 IRQ Interrupt request (XACCL_OFF, upper byte) at the conclusion of the data frame.
Table 7. Generic Master Processor SPI Settings
The master processor initiates the backup function by setting
Processor Setting Description
GLOB_CMD[3] = 1 (DIN = 0xBE08). This command copies Master The ADIS16365 operates as a slave the user registers into their assigned flash memory locations SCLK Rate ≤ 2 MHz1 Normal mode, SMPL_PRD[7:0] ≤ 0x09 and requires the power supply to stay within its normal operating SPI Mode 3 CPOL = 1 (polarity), CPHA = 1 (phase) range for the entire 50 ms process. The FLASH_CNT register MSB First Mode Bit sequence provides a running count of these events for monitoring the 16-Bit Mode Shift register/data length long-term reliability of the flash memory. 1 For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz.
CS SCLK DIN R/W A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 R/W A6 A5 DOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 NOTES 1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]
1
IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.
01 0-
2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.
57 07 Figure 11. SPI Communication Bit Sequence Rev. F | Page 10 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC OPERATION READING SENSOR DATA DEVICE CONFIGURATION MEMORY MAP BURST READ DATA COLLECTION OUTPUT DATA REGISTERS CALIBRATION Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) OPERATIONAL CONTROL Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range INPUT/OUTPUT FUNCTIONS General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC DIAGNOSTICS Self-Test Memory Test Status Alarm Registers PRODUCT IDENTIFICATION APPLICATIONS INFORMATION INSTALLATION AND HANDLING GYROSCOPE BIAS OPTIMIZATION INPUT ADC CHANNEL PC-BASED EVALUATION TOOLS X-RAY SENSITIVITY OUTLINE DIMENSIONS ORDERING GUIDE