Product Brief PIC16(L)F1885X/7X (Microchip) - 8
| Manufacturer | Microchip |
| Description | Full-Featured 28/40-Pin Microcontroller |
| Pages / Page | 16 / 8 — DAC Comparators Zero-Cross Detect MSSP (SPI/I2C™) EUSART DSM Timers/SMT … |
| File Format / Size | PDF / 184 Kb |
| Document Language | English |
DAC Comparators Zero-Cross Detect MSSP (SPI/I2C™) EUSART DSM Timers/SMT CCP and PWM CWG — — — — — — — T1G(1)
Model Line for this Datasheet
- PIC16F18857-E/ML PIC16F18857-E/MLVAO PIC16F18857-E/SO PIC16F18857-E/SP PIC16F18857-E/SS PIC16F18857-E/SSVAO PIC16F18857-I/ML PIC16F18857-I/SO PIC16F18857-I/SP PIC16F18857-I/SS PIC16F18857-I/SSVAO PIC16F18857T-E/MLVAO PIC16F18857T-E/SS PIC16F18857T-E/SSVAO PIC16F18857T-I/ML PIC16F18857T-I/SO PIC16F18857T-I/SS PIC16F18857T-I/SSC02 PIC16F18857T-I/SSVAO PIC16LF18857-E/ML PIC16LF18857-E/SO PIC16LF18857-E/SP PIC16LF18857-E/SS PIC16LF18857-I/ML PIC16LF18857-I/SO PIC16LF18857-I/SP PIC16LF18857-I/SS PIC16LF18857T-I/ML PIC16LF18857T-I/SO PIC16LF18857T-I/SS
- PIC16F18877-E/ML PIC16F18877-E/MV PIC16F18877-E/MVVAO PIC16F18877-E/P PIC16F18877-E/PT PIC16F18877-I/ML PIC16F18877-I/MV PIC16F18877-I/P PIC16F18877-I/PREL PIC16F18877-I/PT PIC16F18877T-E/MV PIC16F18877T-E/MVVAO PIC16F18877T-I/ML PIC16F18877T-I/MV PIC16F18877T-I/PT PIC16LF18877-E/ML PIC16LF18877-E/MV PIC16LF18877-E/P PIC16LF18877-E/PT PIC16LF18877-I/ML PIC16LF18877-I/MV PIC16LF18877-I/MVC04 PIC16LF18877-I/P PIC16LF18877-I/PT PIC16LF18877T-I/MV PIC16LF18877T-I/MVC04 PIC16LF18877T-I/PT PIC16LF18877T-I/PTC01 PIC16LF18877T-I/PTRA3
Text Version of Document
DAC Comparators Zero-Cross Detect MSSP (SPI/I2C™) EUSART DSM Timers/SMT CCP and PWM CWG — — — — — — — T1G(1)
SMTSIG2(1) CCP3(1) — RB6 27 24 ANB6 — — — — — — — — — — RB7 28 25 ANB7 — DAC1OUT2 — — — — — T6IN (1) Basic Voltage Reference ANB5 Interrupt-on-Change ADC 23 Clock Reference (CLKR) 28-Pin (U)QFN 26 NCO 28-Pin SPDIP/SOIC/SSOP RB5 CLC I/O 28-PIN ALLOCATION TABLE (PIC16(L)F1885X) — — — IOCB5 — CLCIN2(1) — — IOCB6 ICSPCLK (1) — — IOCB7 ICSPDAT Advance Information — — CLCIN3 — — — — — IOCC0 SOSCO RC0 11 6 ANC0 — — — — — — — T1CKI(1)
T3CKI(1)
T3G(1)
SMTWIN1(1) RC1 12 9 ANC1 — — — — — — — SMTSIG1(1) CCP2(1) — — — — IOCC1 SOSCI RC2 13 10 ANC2 — — — — — — — T5CKI(1) CCP1(1) — — — — IOCC2 — — SCL1(3,4)
(1) — — T2IN(1) — — — — — IOCC3 — — — — — IOCC4 — RC3 14 11 ANC3 — — — SCK1 2014 Microchip Technology Inc. RC4 15 12 ANC4 — — — — SDA1(3,4)
SDI1(1) — — — — RC5 16 13 ANC5 — — — — — — — T4IN(1) — — — — — IOCC5 — RC6 17 14 ANC6 — — — — — CK(3) — — — — — — — IOCC6 — RC7 18 15 ANC7 — — — — — RX(1)
DT(3) — — — — — — — IOCC7 — RE3 1 26 — — — — — — — — — — — — — — IOCE3 MCLR
VPP VDD 20 17 — — — — — — — — — — — — — — — — VSS 8,
19 5,
16 — — — — — — — — — — — — — — — — Note 1:
2:
3:
4: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 5 for details on which PORT pins may
be used for this signal.
All output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 6.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C™ logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but
input logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F1885X/7X DS40001768A-page 8 TABLE 3:
SMTSIG2(1) CCP3(1) — RB6 27 24 ANB6 — — — — — — — — — — RB7 28 25 ANB7 — DAC1OUT2 — — — — — T6IN (1) Basic Voltage Reference ANB5 Interrupt-on-Change ADC 23 Clock Reference (CLKR) 28-Pin (U)QFN 26 NCO 28-Pin SPDIP/SOIC/SSOP RB5 CLC I/O 28-PIN ALLOCATION TABLE (PIC16(L)F1885X) — — — IOCB5 — CLCIN2(1) — — IOCB6 ICSPCLK (1) — — IOCB7 ICSPDAT Advance Information — — CLCIN3 — — — — — IOCC0 SOSCO RC0 11 6 ANC0 — — — — — — — T1CKI(1)
T3CKI(1)
T3G(1)
SMTWIN1(1) RC1 12 9 ANC1 — — — — — — — SMTSIG1(1) CCP2(1) — — — — IOCC1 SOSCI RC2 13 10 ANC2 — — — — — — — T5CKI(1) CCP1(1) — — — — IOCC2 — — SCL1(3,4)
(1) — — T2IN(1) — — — — — IOCC3 — — — — — IOCC4 — RC3 14 11 ANC3 — — — SCK1 2014 Microchip Technology Inc. RC4 15 12 ANC4 — — — — SDA1(3,4)
SDI1(1) — — — — RC5 16 13 ANC5 — — — — — — — T4IN(1) — — — — — IOCC5 — RC6 17 14 ANC6 — — — — — CK(3) — — — — — — — IOCC6 — RC7 18 15 ANC7 — — — — — RX(1)
DT(3) — — — — — — — IOCC7 — RE3 1 26 — — — — — — — — — — — — — — IOCE3 MCLR
VPP VDD 20 17 — — — — — — — — — — — — — — — — VSS 8,
19 5,
16 — — — — — — — — — — — — — — — — Note 1:
2:
3:
4: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 5 for details on which PORT pins may
be used for this signal.
All output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 6.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C™ logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but
input logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F1885X/7X DS40001768A-page 8 TABLE 3:
