Datasheet ARG81800 (Allegro) - 9
| Manufacturer | Allegro |
| Description | 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD |
| Pages / Page | 42 / 9 — 40 V, 500 mA / 1.0 A Synchronous Buck Regulators. ARG81800. with Ultralow … |
| File Format / Size | PDF / 4.0 Mb |
| Document Language | English |
40 V, 500 mA / 1.0 A Synchronous Buck Regulators. ARG81800. with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
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40 V, 500 mA / 1.0 A Synchronous Buck Regulators ARG81800 with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit OUTPUT VOLTAGE PROTECTION THRESHOLDS (VFB, OV, UV)
VFB OV PWM Threshold VFB(OV) VFB rising 850 880 900 mV VFB OV PWM Hysteresis VFB(OV,HYS) VFB falling, relative to VFB(OV) – −15 – mV VFB UV PWM Threshold VFB(UV) VFB falling 716 740 764 mV VFB UV PWM Hysteresis VFB(UV,HYS) VFB rising, relative to VFB(UV) – +15 – mV VFB UV LP Mode Threshold [3] VFB(UV,LP) VFB falling 665 700 735 mV
POWER GOOD OUTPUT (PGOOD PIN)
PGOOD Startup (SU) Delay tdPG(SU) Increasing VFB due to startup − 30 − µs PGOOD Undervoltage (UV) Delay tdPG(UV) Decreasing VFB − 30 − µs PGOOD Overvoltage (OV) Delay tdPG(OV) After an overvoltage event − 240 − fSW cycles PGOOD Low Voltage VPG(L) IPGOOD = 5 mA − 200 400 mV PGOOD Leakage [1] IPG(LKG) VPGOOD = 5.5 V − − 2 µA
PWM/AUTO INPUT
PWM/AUTO High Threshold VHI(PWM) VPWM/AUTO rising 1.8 2.0 2.5 V PWM/AUTO Float Voltage VFLOAT(PWM) VPWM/AUTO floating 1.1 1.4 1.7 V PWM/AUTO Low Threshold VLO(PWM) VPWM/AUTO falling 0.6 0.8 1.0 V PWM to LP Transition Delay [3] t VPWM/AUTO = 0 V, VSS > VHIC/LP(EN), dPWM(LP) PGOOD high − 7.5 − ms
ENABLE INPUT (EN PIN)
Enable High Threshold VENHI VEN rising − 1.6 2.0 V Enable Low Threshold VENLO VEN falling 0.8 1.4 − V Enable Input Hysteresis VENHYS VENHI ‒ VENLO − 200 − mV Disable Delay t VEN transitions low to when SW stops DISDLY switching − 120 − fSW cycles Enable Pin Input Current IEN VEN = VPWM/AUTO = 5 V − 12 − µA Continued on next page... 9 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing
VFB OV PWM Threshold VFB(OV) VFB rising 850 880 900 mV VFB OV PWM Hysteresis VFB(OV,HYS) VFB falling, relative to VFB(OV) – −15 – mV VFB UV PWM Threshold VFB(UV) VFB falling 716 740 764 mV VFB UV PWM Hysteresis VFB(UV,HYS) VFB rising, relative to VFB(UV) – +15 – mV VFB UV LP Mode Threshold [3] VFB(UV,LP) VFB falling 665 700 735 mV
POWER GOOD OUTPUT (PGOOD PIN)
PGOOD Startup (SU) Delay tdPG(SU) Increasing VFB due to startup − 30 − µs PGOOD Undervoltage (UV) Delay tdPG(UV) Decreasing VFB − 30 − µs PGOOD Overvoltage (OV) Delay tdPG(OV) After an overvoltage event − 240 − fSW cycles PGOOD Low Voltage VPG(L) IPGOOD = 5 mA − 200 400 mV PGOOD Leakage [1] IPG(LKG) VPGOOD = 5.5 V − − 2 µA
PWM/AUTO INPUT
PWM/AUTO High Threshold VHI(PWM) VPWM/AUTO rising 1.8 2.0 2.5 V PWM/AUTO Float Voltage VFLOAT(PWM) VPWM/AUTO floating 1.1 1.4 1.7 V PWM/AUTO Low Threshold VLO(PWM) VPWM/AUTO falling 0.6 0.8 1.0 V PWM to LP Transition Delay [3] t VPWM/AUTO = 0 V, VSS > VHIC/LP(EN), dPWM(LP) PGOOD high − 7.5 − ms
ENABLE INPUT (EN PIN)
Enable High Threshold VENHI VEN rising − 1.6 2.0 V Enable Low Threshold VENLO VEN falling 0.8 1.4 − V Enable Input Hysteresis VENHYS VENHI ‒ VENLO − 200 − mV Disable Delay t VEN transitions low to when SW stops DISDLY switching − 120 − fSW cycles Enable Pin Input Current IEN VEN = VPWM/AUTO = 5 V − 12 − µA Continued on next page... 9 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing
