Datasheet TLS715B0NAV50 (Infineon) - 5

link to page 7
OPTIREG™ Linear TLS715B0NAV50 Low dropout linear voltage regulator Pin configuration 2 Pin configuration 2.1 Pin assignment PG-TSNP-7
GND 1 6 GND Q 2 7 5 I GND 3 4 EN GND
Figure 2 Pin configuration 2.2 Pin definitions and functions PG-TSNP-7 Pin Symbol Function
1 GND
Ground
2 Q
Output
Block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in the table
“Functional range” on Page 7
. 3 GND
Ground
4 EN
Enable
(integrated pull-down resistor) Enable the IC with high level input signal. Disable the IC with low level input signal. 5 I
Input
For compensating line influences, a capacitor to GND close to the IC terminals is recommended. 6 GND
Ground
7 GND
Ground
Datasheet 5 Rev. 1.1 2019-07-31 Document Outline Features Potential applications Product validation Description Table of contents 1 Block diagram 2 Pin configuration 2.1 Pin assignment PG-TSNP-7 2.2 Pin definitions and functions PG-TSNP-7 3 General product characteristics 3.1 Absolute maximum ratings 3.2 Functional range 3.3 Thermal resistance 4 Block description and electrical characteristics 4.1 Voltage regulation 4.2 Typical performance characteristics voltage regulator 4.3 Current consumption 4.4 Typical performance characteristics current consumption 4.5 Enable 4.6 Typical performance characteristics enable 5 Application information 5.1 Application diagram 5.2 Selection of external components 5.2.1 Input pin 5.2.2 Output pin 5.3 Thermal considerations 5.4 Reverse polarity protection 5.5 Further application information 6 Package information 7 Revision history