Datasheet AD73311L (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | a Low Cost, Low Power CMOS General Purpose Analog Front End |
| Pages / Page | 36 / 4 — AD73311L. Table II. Signal Ranges. Parameter. Condition. Signal Range |
| Revision | A |
| File Format / Size | PDF / 391 Kb |
| Document Language | English |
AD73311L. Table II. Signal Ranges. Parameter. Condition. Signal Range
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Text Version of Document
AD73311L Table II. Signal Ranges Parameter Condition Signal Range
VREFCAP 1.2 V ± 10% VREFOUT 1.2 V ± 10% ADC Maximum Input Range at VIN 1.578 V p-p Nominal Reference Level 1.0954 V p-p DAC Maximum Voltage Output Swing Single-Ended 1.578 V p-p Differential 3.156 V p-p Nominal Voltage Output Swing Single-Ended 1.0954 V p-p Differential 2.1909 V p-p Output Bias Voltage VREFOUT
TIMING CHARACTERISTICS (AVDD = DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
ⴗ
C to +105
ⴗ
C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK
t1 100
A IOL t2 TO OUTPUT 2.1V PIN CL 15pF t 100
A IOH 3
Figure 1. MCLK Timing Figure 2. Load Circuit for Timing Specifications
t1 t2 t3 MCLK t13 SCLK* t5 t6 t4 *SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing –4– REV. A
VREFCAP 1.2 V ± 10% VREFOUT 1.2 V ± 10% ADC Maximum Input Range at VIN 1.578 V p-p Nominal Reference Level 1.0954 V p-p DAC Maximum Voltage Output Swing Single-Ended 1.578 V p-p Differential 3.156 V p-p Nominal Voltage Output Swing Single-Ended 1.0954 V p-p Differential 2.1909 V p-p Output Bias Voltage VREFOUT
TIMING CHARACTERISTICS (AVDD = DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
ⴗ
C to +105
ⴗ
C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK
t1 100
A IOL t2 TO OUTPUT 2.1V PIN CL 15pF t 100
A IOH 3
Figure 1. MCLK Timing Figure 2. Load Circuit for Timing Specifications
t1 t2 t3 MCLK t13 SCLK* t5 t6 t4 *SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing –4– REV. A
