Datasheet AD73311L (Analog Devices) - 10

AD73311L ADC Coding
The ADC coding scheme is in twos complement format (see Figure 8). The output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, which is the 16-bit transfer being used as a flag bit to indicate either control or data in the frame.
FB = 4kHz FSINIT = DMCLK/8
a. Analog Antialias Filter Transfer Function
VINN VREF + (VREF
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0.32875) SIGNAL TRANSFER FUNCTION ANALOG VREF INPUT NOISE TRANSFER FUNCTION VREF – (VREF
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0.32875) VINP 10...00 00...00 01...11 FB = 4kHz FSINIT = DMCLK/8 ADC CODE DIFFERENTIAL
b. Analog Sigma-Delta Modulator Transfer Function
VREF + (VREF
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0.6575) VINN ANALOG VREF INPUT VREF – (VREF
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0.6575) VINP FB = 4kHz FSINTER = DMCLK/256 10...00 00...00 01...11
c. Digital Decimator Transfer Function
ADC CODE SINGLE-ENDED
Figure 8. ADC Transfer Function
Decoder Channel
The decoder channel consists of a digital interpolator, digital sigma-delta modulator, a single bit digital-to-analog converter (DAC), an analog smoothing filter and a programmable gain amplifier with differential output.
DAC Coding FB = 4kHz FSFINAL = 8kHz FSINTER = DMCLK/256
The DAC coding scheme is in twos complement format with d. Final Filter LPF (HPF) Transfer Function 0x7FFF being full-scale positive and 0x8000 being full-scale Figure 7. AD73311L ADC Frequency Responses negative.
Decimation Filter Interpolation Filter
The digital filter used in the AD73311L carries out two impor- The anti-imaging interpolation filter is a sinc-cubed digital filter tant functions. Firstly, it removes the out-of-band quantization which up-samples the 16-bit input words from the SPORT noise, which is shaped by the analog modulator and secondly, it input rate of DMCLK/M (where M depends on the sample rate decimates the high frequency bitstream to a lower rate 15-bit word. setting—M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @ The antialiasing decimation filter is a sinc-cubed digital filter 16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while that reduces the sampling rate from DMCLK/8 at the modula- filtering to attenuate images produced by the interpolation pro- tor to an output rate at the SPORT of DMCLK/M (where M cess. Its Z transform is given as: [(1–Z–N)/(1–Z–1)]3 where N is depends on the sample rate setting—M = 256 @ 64 kHz; M = determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @ 512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and 32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC increases the resolution from a single bit to 15 bits. Its Z trans- receives 16-bit samples from the host DSP processor at a rate of form is given as: [(1–Z–N)/(1–Z–1)]3 where N is determined by DMCLK/M. If the host processor fails to write a new value to the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N = the serial port, the existing (previous) data is read again. The 128 @ 16 kHz, N = 256 @ 8 kHz). This ensures a minimal data stream is filtered by the anti-imaging interpolation filter, group delay of 25 µs at the 64 kHz sampling rate. but there is an option to bypass the interpolator for the mini- mum group delay configuration by setting the IBYP bit (CRE:5) of Control Register E. The interpolation filter has the same charac- teristics as the ADC’s antialiasing decimation filter. –10– REV. A