Datasheet PI6CG33401 (Diodes) - 8
| Manufacturer | Diodes |
| Description | 3.3V Very-Low-Power 4-Output PCIe Clock Generator With On-Chip Termination |
| Pages / Page | 23 / 8 — PI6CG33401. LVCMOS AC Characteristics. Symbol Parameters. Conditions. … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
PI6CG33401. LVCMOS AC Characteristics. Symbol Parameters. Conditions. Min. Typ. Max. Units. Note:
Model Line for this Datasheet
Text Version of Document
A product Line of Diodes Incorporated
PI6CG33401 LVCMOS AC Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Conditions Min. Typ. Max. Units
fINPUT Input Frequency XTAL_IN/CLK — 25 — MHz tRIN Input Rise Time Single-ended inputs — — 5 ns tFIN Input Fall Time Single-ended inputs — — 5 ns tSTAB Clock Stabilization From power up and after input clock stabi- lization or deassertion of PD# to first clock — 0.75 1 ms Q start after OE# assertion tOELAT Output Enable Latency 1 — 3 clocks Q stop after OE# deassertion tPDLAT PD# Deassertion Differential outputs enable after PD# deassertion — 20 300 µs tPERIOD REFOUT Clock Period REFOUT, assume input is at 25MHz — 40 — ns fACC REFOUT Frequency Accuracy 1 REFOUT, long term accuracy to input — 0 — ppm Byte 3 = 1F, 20% to 80% of VDDREF 0.9 1.4 2 V/ns Byte 3 = 5F, 20% to 80% of V t DDREF 1.5 2.4 3.2 V/ns SLEW REFOUT Slew Rate 1 Byte 3 = 9F, 20% to 80% of VDDREF 2.0 3.0 3.8 V/ns Byte 3 = DF, 20% to 80% of VDDREF 2.3 3.2 4 V/ns tDC REFOUT Duty Cycle 1 VT = VDD /2V, driven by a Xtal 45 50 55 % tDCDIS REFOUT Duty Cycle Distortion VT = VDD /2V, driven by an external source -2 0 +2 % tJITCC REFOUT Cycle-Cycle Jitter VT = VDD /2V, driven by a Xtal — 70 150 ps 12kHz to 5MHz, SSC off, driven by a Xtal — 0.16 0.3 ps tJITPH REFOUT Phase Jitter, RMS 12kHz to 5MHz, SSC on, driven by a Xtal — 0.9 1.5 ps 1kHz offset, driven by a Xtal — -149 -135 dBc/ Hz tJITN Noise Floor 10kHz offset to Nyquist, driven by a Xtal — -158 -140 dBc/ Hz
Note:
1. Guaranteed by design and characterization—not 100% tested in production. PI6CG33401 Document Number DS41072 Rev 4-2 8 www.diodes.com September 2019 Diodes Incorporated
PI6CG33401 LVCMOS AC Characteristics
Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions
Symbol Parameters Conditions Min. Typ. Max. Units
fINPUT Input Frequency XTAL_IN/CLK — 25 — MHz tRIN Input Rise Time Single-ended inputs — — 5 ns tFIN Input Fall Time Single-ended inputs — — 5 ns tSTAB Clock Stabilization From power up and after input clock stabi- lization or deassertion of PD# to first clock — 0.75 1 ms Q start after OE# assertion tOELAT Output Enable Latency 1 — 3 clocks Q stop after OE# deassertion tPDLAT PD# Deassertion Differential outputs enable after PD# deassertion — 20 300 µs tPERIOD REFOUT Clock Period REFOUT, assume input is at 25MHz — 40 — ns fACC REFOUT Frequency Accuracy 1 REFOUT, long term accuracy to input — 0 — ppm Byte 3 = 1F, 20% to 80% of VDDREF 0.9 1.4 2 V/ns Byte 3 = 5F, 20% to 80% of V t DDREF 1.5 2.4 3.2 V/ns SLEW REFOUT Slew Rate 1 Byte 3 = 9F, 20% to 80% of VDDREF 2.0 3.0 3.8 V/ns Byte 3 = DF, 20% to 80% of VDDREF 2.3 3.2 4 V/ns tDC REFOUT Duty Cycle 1 VT = VDD /2V, driven by a Xtal 45 50 55 % tDCDIS REFOUT Duty Cycle Distortion VT = VDD /2V, driven by an external source -2 0 +2 % tJITCC REFOUT Cycle-Cycle Jitter VT = VDD /2V, driven by a Xtal — 70 150 ps 12kHz to 5MHz, SSC off, driven by a Xtal — 0.16 0.3 ps tJITPH REFOUT Phase Jitter, RMS 12kHz to 5MHz, SSC on, driven by a Xtal — 0.9 1.5 ps 1kHz offset, driven by a Xtal — -149 -135 dBc/ Hz tJITN Noise Floor 10kHz offset to Nyquist, driven by a Xtal — -158 -140 dBc/ Hz
Note:
1. Guaranteed by design and characterization—not 100% tested in production. PI6CG33401 Document Number DS41072 Rev 4-2 8 www.diodes.com September 2019 Diodes Incorporated
