Datasheet ADT7312 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Automotive, ±1°C Accurate, 16-Bit, 175°C Digital SPI Temperature Sensor in Die Form |
| Pages / Page | 24 / 4 — ADT7312. Data Sheet. SPI TIMING SPECIFICATIONS. Table 2. Parameter1, 2. … |
| Revision | A |
| File Format / Size | PDF / 540 Kb |
| Document Language | English |
ADT7312. Data Sheet. SPI TIMING SPECIFICATIONS. Table 2. Parameter1, 2. Limit at TMIN, TMAX. Unit. Description. SCLK. MSB. LSB. DIN. DOUT
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ADT7312 Data Sheet SPI TIMING SPECIFICATIONS
TA = −55°C to +175°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2. Parameter1, 2 Limit at TMIN, TMAX Unit Description
t1 0 ns min CS falling edge to SCLK active edge setup time t2 100 ns min SCLK high pulse width t3 100 ns min SCLK low pulse width t4 30 ns min Data setup time prior to SCLK rising edge t5 25 ns min Data hold time after SCLK rising edge t6 5 ns min Data access time after SCLK falling edge 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t 3 7 10 ns min Bus relinquish time after CS inactive edge 80 ns max t8 0 ns min SCLK inactive edge to CS rising edge hold time t9 0 ns min CS falling edge to DOUT active time 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t10 10 ns min SCLK inactive edge to DOUT low 1 Sample tested during initial release to ensure compliance. 2 See Figure 2. 3 The t7 values are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
CS t1 t2 t t 3 8 1 2 3 6 7 8 9 10 23 24 SCLK t4 t5 MSB LSB DIN t6 t t 10 9 DOUT MSB LSB
002
t7
06791- Figure 2. Detailed SPI Timing Diagram Rev. A | Page 4 of 24 Document Outline Features Applications General Description Product Highlights Functional Block Diagram Table of Contents Revision History Specifications SPI Timing Specifications Absolute Maximum Ratings ESD Caution Pad Configuration and Function Descriptions Die Bond Pad Coordinates Typical Performance Characteristics Theory of Operation Circuit Description Converter Architecture Normal Mode (Continuous Conversion Mode) One-Shot Mode CT and INT Operation in One-Shot Mode 1 SPS Mode Shutdown Mode Fault Queue Temperature Data Format Temperature Conversion Formulas 16-Bit Temperature Data Format 13-Bit Temperature Data Format 10-Bit Temperature Data Format 9-Bit Temperature Data Format Registers Status Register Configuration Register Temperature Value Register ID Register TCRIT Setpoint Register THYST Setpoint Register THIGH Setpoint Register TLOW Setpoint Register Serial Interface SPI Command Byte Writing Data Reading Data Interfacing to DSPs or Microcontrollers Resetting the Serial Interface INT and CT Outputs Undertemperature and Overtemperature Detection Comparator Mode Interrupt Mode Redundant Critical Generator Applications Information Thermal Response Time Supply Decoupling Powering from a Switching Regulator Temperature Monitoring Quick Guide to Measuring Temperature Outline Dimensions Ordering Guide Automotive Products
ADT7312 Data Sheet SPI TIMING SPECIFICATIONS
TA = −55°C to +175°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2. Parameter1, 2 Limit at TMIN, TMAX Unit Description
t1 0 ns min CS falling edge to SCLK active edge setup time t2 100 ns min SCLK high pulse width t3 100 ns min SCLK low pulse width t4 30 ns min Data setup time prior to SCLK rising edge t5 25 ns min Data hold time after SCLK rising edge t6 5 ns min Data access time after SCLK falling edge 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t 3 7 10 ns min Bus relinquish time after CS inactive edge 80 ns max t8 0 ns min SCLK inactive edge to CS rising edge hold time t9 0 ns min CS falling edge to DOUT active time 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t10 10 ns min SCLK inactive edge to DOUT low 1 Sample tested during initial release to ensure compliance. 2 See Figure 2. 3 The t7 values are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
CS t1 t2 t t 3 8 1 2 3 6 7 8 9 10 23 24 SCLK t4 t5 MSB LSB DIN t6 t t 10 9 DOUT MSB LSB
002
t7
06791- Figure 2. Detailed SPI Timing Diagram Rev. A | Page 4 of 24 Document Outline Features Applications General Description Product Highlights Functional Block Diagram Table of Contents Revision History Specifications SPI Timing Specifications Absolute Maximum Ratings ESD Caution Pad Configuration and Function Descriptions Die Bond Pad Coordinates Typical Performance Characteristics Theory of Operation Circuit Description Converter Architecture Normal Mode (Continuous Conversion Mode) One-Shot Mode CT and INT Operation in One-Shot Mode 1 SPS Mode Shutdown Mode Fault Queue Temperature Data Format Temperature Conversion Formulas 16-Bit Temperature Data Format 13-Bit Temperature Data Format 10-Bit Temperature Data Format 9-Bit Temperature Data Format Registers Status Register Configuration Register Temperature Value Register ID Register TCRIT Setpoint Register THYST Setpoint Register THIGH Setpoint Register TLOW Setpoint Register Serial Interface SPI Command Byte Writing Data Reading Data Interfacing to DSPs or Microcontrollers Resetting the Serial Interface INT and CT Outputs Undertemperature and Overtemperature Detection Comparator Mode Interrupt Mode Redundant Critical Generator Applications Information Thermal Response Time Supply Decoupling Powering from a Switching Regulator Temperature Monitoring Quick Guide to Measuring Temperature Outline Dimensions Ordering Guide Automotive Products
