Datasheet ADT7310 (Analog Devices) - 4

ManufacturerAnalog Devices
Description±0.5°C Accurate, 16-Bit Digital SPI Temperature Sensor
Pages / Page24 / 4 — ADT7310. Data Sheet. SPI TIMING SPECIFICATIONS. Table 2. Parameter. 1, 2 …
RevisionA
File Format / SizePDF / 403 Kb
Document LanguageEnglish

ADT7310. Data Sheet. SPI TIMING SPECIFICATIONS. Table 2. Parameter. 1, 2 Limit. TMIN, TMAX (B Version). Unit. Conditions/Comments. SCLK

ADT7310 Data Sheet SPI TIMING SPECIFICATIONS Table 2 Parameter 1, 2 Limit TMIN, TMAX (B Version) Unit Conditions/Comments SCLK

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ADT7310 Data Sheet SPI TIMING SPECIFICATIONS
TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2. Parameter 1, 2 Limit at TMIN, TMAX (B Version) Unit Conditions/Comments
t1 0 ns min CS falling edge to SCLK active edge setup time3 t2 100 ns min SCLK high pulse width t3 100 ns min SCLK low pulse width t4 30 ns min Data valid to SCLK edge setup time t5 25 ns min Data valid to SCLK edge hold time t6 0 ns min SCLK active edge to data valid delay3 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t 4 7 10 ns min Bus relinquish time after CS inactive edge 80 ns max t8 0 ns min CS rising edge to SCLK edge hold time t9 0 ns min CS falling edge to DOUT active time 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t10 10 ns min SCLK inactive edge to DOUT high 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 2. 3 SCLK active edge is falling edge of SCLK. 4 This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
CS t1 t2 t t 3 8 1 2 3 7 8 SCLK 1 2 7 8 t4 t5 MSB LSB DIN t10 t6 t7 t9
2 00 9-
DOUT MSB LSB
78 07 Figure 2. Detailed SPI Timing Diagram
ISINK (1.6mA WITH VDD = 5V, 100µA WITH VDD = 3V) TO OUTPUT 1.6V PIN 10pF I
04
SOURCE (200µA WITH VDD = 5V,
0 9-
100µA WITH VDD = 3V)
78 07 Figure 3. Load Circuit for Timing Characterization Rev. A | Page 4 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications SPI Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Information Converter Details Temperature Measurement One-Shot Mode 1 SPS Mode CT and INT Operation in One-Shot Mode Continuous Read Mode Shutdown Fault Queue Temperature Data Format Temperature Conversion Formulas 16-Bit Temperature Data Format 13-Bit Temperature Data Format 10-Bit Temperature Data Format 9-Bit Temperature Data Format Registers Status Register Configuration Register Temperature Value Register ID Register TCRIT Setpoint Register THYST Setpoint Register THIGH Setpoint Register TLOW Setpoint Register Serial Interface SPI Command Byte Writing Data Reading Data Interfacing to DSPs or Microcontrollers Serial Interface Reset INT and CT Outputs Undertemperature and Overtemperature Detection Comparator Mode Interrupt Mode Applications Information Thermal Response Time Supply Decoupling Temperature Monitoring Outline Dimensions Ordering Guide