Datasheet ADT7517-KGD (Analog Devices) - 9

Known Good Die ADT7517-KGD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 19 18 17 16 15 1 2 3 4 5 6 14 7 13 12 8 11 9 10
006 10686- Figure 6. Pad Configuration
Table 5. Pad Function Descriptions X-Axis Y-Axis Pad No. (µm) (µm) Mnemonic Description
1 −764 +763 VREF-IN Reference Input Pad for All Four DACs. This input is buffered and has an input range from 1 V to VDD. 2 −764 +608 CS SPI Active Low Control Input. CS is the frame synchronization signal for the input data. When CS goes low, it enables the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial clocks. It is recommended that this pad be tied high to VDD when operating the serial interface in I2C mode. 3 −764 +305 GND Analog Ground. 4 −764 +155 GND Analog Ground. 5 −764 +1 GND Analog Ground. 6 −764 −152 VDD Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground. 7 −764 −306 VDD Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground. 8 −764 −502 D+/AIN1 Positive Connection to External Temperature Sensor (D+). Analog Input (AIN1). Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD. 9 −764 −1045 D−/AIN2 Negative Connection to External Temperature Sensor (D−). Analog Input (AIN2). Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD. 10 +764 −1045 LDAC/AIN3 Active Low Control Input (LDAC). Transfers the contents of the input registers to their respective DAC registers. A falling edge on this pad forces any or all DAC registers to be updated if the input registers have new data. A minimum pulse width of 20 ns must be applied to the LDAC pad to ensure proper loading of a DAC register. LDAC allows the simultaneous updating of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pad. By default, the LDAC pad controls the loading of the DAC registers. Analog Input (AIN3). Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to VDD. 11 +764 −579 INT/INT Over Limit Interrupt. The output polarity of this pad can be set to provide an active low or active high interrupt when temperature, VDD, or AIN limits are exceeded. The default is active low. This open-drain output requires a pull-up resistor. 12 +764 −425 DOUT/ADD SPI Serial Data Output (DOUT). Logic output. Data is clocked out of any register at this pad on the falling edge of SCLK. This open-drain output requires a pull-up resistor. I2C Serial Bus Address Selection Pad (ADD). Logic input. When this pad is low, the I2C address is set to 1001 000; when the pad is left floating, the I2C address is set to 1001 010; when the pad is high, the I2C address is set to 1001 011. The I2C address set by the ADD pad is not latched by the device until after the address is sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. Any subsequent change on this pad has no effect on the I2C serial bus address. Rev. A | Page 9 of 11 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DAC AC CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE